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We use 2 tda4-evm boards to test the SGMII feasibility on the PORT 2 (SERDES 0 Lan1)with SDK V7.2.
I reference resources https://e2e.ti.com/support/processors/f/processors-forum/936840/faq-dra829vxevm-is-it-possible-to-connect-two-dra829-evms-via-sgmii to debug the driver
I change configuration parameters exactly the same as the example provided by ti “MAC_MAC_SGMII_1G_Linux.zip ”
beause of the sdk7.0 and sdk 7.2 have some different i make some change:
diff -urN /home/hao.luo/tda4/720a/ra/pdk_jacinto_07_01_05_14/packages/ti/board/src/j721e_evm/board_ethernet_config.c /home/hao.luo/tda4/720b/ra/pdk_jacinto_07_01_05_14/packages/ti/board/src/j721e_evm/board_ethernet_config.c
--- /home/hao.luo/tda4/720a/ra/pdk_jacinto_07_01_05_14/packages/ti/board/src/j721e_evm/board_ethernet_config.c 2021-05-29 11:18:25.642181435 +0800
+++ /home/hao.luo/tda4/720b/ra/pdk_jacinto_07_01_05_14/packages/ti/board/src/j721e_evm/board_ethernet_config.c 2021-05-31 14:22:21.087563004 +0800
@@ -709,8 +709,18 @@
/* Configures the CPSW9G RGMII ports */
for(portNum=0; portNum < BOARD_CPSW9G_PORT_MAX; portNum++)
{
- status = Board_cpsw9gEthConfig(portNum, RGMII);
+
+if(1 == portNum)
+{
+
+status = Board_cpsw9gEthConfig(portNum, SGMII);
+}
+else
+{
+
+ status = Board_cpsw9gEthConfig(portNum, RGMII);
+}
if(status != BOARD_SOK)
{
return BOARD_FAIL;
--- /home/hao.luo/tda4/720a/ra/pdk_jacinto_07_01_05_14/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c 2021-05-29 11:18:35.582181509 +0800
+++ /home/hao.luo/tda4/720b/ra/pdk_jacinto_07_01_05_14/packages/ti/drv/enet/examples/utils/V1/enet_appboardutils_j721e_evm.c 2021-06-01 14:45:18.336222673 +0800
@@ -310,7 +310,8 @@
EnetBoard_enetExpCfg();
#endif
-#if !defined(ENETAPPUTILS_BYPASS_QSGMII) && defined(BUILD_MCU2_0)
+//#if !defined(ENETAPPUTILS_BYPASS_QSGMII) && defined(BUILD_MCU2_0)
+#if defined (BUILD_MCU2_0)
#if defined (SOC_J721E)
/* On J721E EVM, port 1 (SERDES0, lane 1) is brought for SGMII */
EnetBoard_configSierra0Clks();
@@ -535,7 +536,7 @@
Board_STATUS boardStatus;
Enet_Type enetType;
uint32_t instId;
-
+
/* Override the ENET control set by board lib */
#if defined (SOC_J721E)
EnetAppUtils_assert(portNum == ENET_MAC_PORT_2);
@@ -549,20 +550,23 @@
/* Override the ENET control set by board lib */
EnetBoard_setEnetControl(enetType, instId, portNum, SGMII);
-
boardStatus = Board_serdesCfgSgmii();
EnetAppUtils_assert(boardStatus == BOARD_SOK);
-
EnetPhy_initCfg(phyCfg);
- phyCfg->phyAddr = EnetBoard_getSgmiiPhyAddr();
- phyCfg->skipExtendedCfg = true;
-
+ //phyCfg->phyAddr = EnetBoard_getSgmiiPhyAddr();
+ //phyCfg->skipExtendedCfg = true;
+ phyCfg->phyAddr = ENETPHY_INVALID_PHYADDR;
/* RGMII interface type */
interface->layerType = ENET_MAC_LAYER_GMII;
interface->sublayerType = ENET_MAC_SUBLAYER_SERIAL;
interface->variantType = ENET_MAC_VARIANT_NONE;
- macCfg->sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY;
+// macCfg->sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_WITH_PHY;
+
+//macCfg->sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_AUTONEG_MASTER;
+ macCfg->sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_AUTONEG_SLAVE;
+// macCfg->sgmiiMode = ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK;
+EnetAppUtils_print("SGMII set phy config ok!!!\n");
}
void EnetBoard_setPhyConfigQsgmii(Enet_Type enetType,
@@ -729,13 +733,25 @@
break;
case ENET_CPSW_9G:
- EnetBoard_setPhyConfigRgmii(enetType,
+
+ if(ENET_MAC_PORT_2 == portNum)
+ {
+
+ EnetBoard_setPhyConfigSgmii(portNum,
+ macCfg,
+ interface,
+ phyCfg);
+ }
+ else
+ {
+
+ EnetBoard_setPhyConfigRgmii(enetType,
portNum,
macCfg,
interface,
phyCfg);
-
+ }
break;
default:
--- /home/hao.luo/tda4/720a/ra/pdk_jacinto_07_01_05_14/packages/ti/csl/src/ip/serdes_cd/V0/csl_serdes3.c 2021-05-29 11:18:24.478181426 +0800
+++ /home/hao.luo/tda4/720b/ra/pdk_jacinto_07_01_05_14/packages/ti/csl/src/ip/serdes_cd/V0/csl_serdes3.c 2021-05-31 20:36:23.103731662 +0800
@@ -262,7 +262,14 @@
if(refClk >= CSL_SERDES_REF_CLOCK_100M) /* 100MHz and greater reference clock */
{
CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.SERDES_TOP_CTRL),29,28,0x1);
- }
+// add modified 3 line directly change register
+
+ CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.SERDES_TOP_CTRL),31,30,0x0);
+
+ CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.LANECTL0),25,24,0x0);
+
+ CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.LANALIGN0),5,0,0x0);
+ }
else /* Less than 100MHz reference clock */
{
CSL_FINSR(*(volatile uint32_t *)(uintptr_t)(&sierra_sds_reg->WIZ_CONFIG.SERDES_TOP_CTRL),29,28,0x3);
--- /home/hao.luo/tda4/720a/ra/vision_apps/utils/ethfw/src/app_ethfw.c 2021-05-29 11:19:39.614181991 +0800
+++ /home/hao.luo/tda4/720b/ra/vision_apps/utils/ethfw/src/app_ethfw.c 2021-05-31 18:40:25.539679374 +0800
@@ -88,9 +88,9 @@
},
#endif
-#if 0
+#if 1
{
- .portNum = ENET_MAC_PORT_4, /* RGMII */
+ .portNum = ENET_MAC_PORT_2, /* SGMII */
.vlanCfg = { .portPri = 0U, .portCfi = 0U, .portVID = 0U }
},
#endif
diff -urN /home/hao.luo/tda4/7250/la/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts /home/hao.luo/tda4/725/la/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
--- /home/hao.luo/tda4/7250/la/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts 2021-05-29 12:01:32.850200878 +0800
+++ /home/hao.luo/tda4/725/la/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts 2021-06-01 14:46:09.956223060 +0800
@@ -831,6 +926,11 @@
};
};
+
+&serdes_wiz0 {
+ status = "disabled";
+};
+
&serdes1 {
serdes1_pcie_link: link@0 {
reg = <0>;
@@ -861,20 +961,22 @@
phys = <&serdes0_pcie_link>;
phy-names = "pcie_phy";
num-lanes = <1>;
+ status = "disabled";
};
@@ -915,8 +1017,7 @@
};
&serdes_ln_ctrl {
- idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
- <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ idle-states = <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
diff -urN /home/hao.luo/tda4/720a/la/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi /home/hao.luo/tda4/720b/la/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
--- /home/hao.luo/tda4/720a/la/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi 2021-05-29 12:01:32.562200876 +0800
+++ /home/hao.luo/tda4/720b/la/board-support/linux-5.4.74+gitAUTOINC+9574bba32a-g9574bba32a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi 2021-05-29 15:55:55.886306566 +0800
@@ -53,14 +53,12 @@
serdes_ln_ctrl: serdes_ln_ctrl@4080 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
- mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
- <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ mux-reg-masks = <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
<0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
<0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
<0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
/* SERDES4 lane0/1/2/3 select */
- idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
- <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ idle-states = <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
<SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
bug it's does not have any log when i run /ti_fs/vision_app/vision_app_init.sh only print 5.184868 s: CPSW_9G Test on MAIN NAVSS ，，，，No other information
It looks like it's stuck somewhere.
So I use CCS debug it,and found it's in a dead cycle at the pdk_jacinto_07_01_05_14/packages/ti/drv/enet/src/mod/cpsw_macport.c @line2258-2269
static int32_t CpswMacPort_checkSgmiiAutoNegStatus(CSL_CpsgmiiRegs *sgmiiRegs,
Enet_MacPort macPort)
{
CSL_SGMII_STATUS sgmiiStatus;
uint32_t portNum = ENET_MACPORT_NORM(macPort);
uint32_t portId = ENET_MACPORT_ID(macPort);
int32_t status = ENET_SOK;
ENETTRACE_VAR(portId);
/* Wait for SGMII Autonegotiation to complete without error */
do
{
CSL_SGMII_getStatus(sgmiiRegs, portNum, &sgmiiStatus);
if (sgmiiStatus.bIsAutoNegError != 0U)
{
/* Auto-negotiation error */
ENETTRACE_ERR("MAC %u: SGMII auto-negotiation failed: %d\n", portId, status);
status = ENET_EFAIL;
break;
}
}
while (sgmiiStatus.bIsAutoNegComplete != 1U);
One board is set to master and the other is slave.But it seems that the self negotiation has not been completed
If I set macCfg->sgmiiMode to ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK,the program will stuck at the line 2192-2196 in pdk_jacinto_07_01_05_14\packages\ti\drv\enet\src\mod\cpsw_macport.c because sgmiiStatus.bIsLinkUp is always 0.
I configured the SGMII support similar to this E2E thread:
I have a question. If there is a problem with the TX and Rx lines between the 2 tda4 set to ENET_MAC_SGMIIMODE_SGMII_FORCEDLINK, will this happen?
