TDA2SX: TDA2SX EVE CPU ENABLE PEME PARITY

Below are quoted from TRM, and literally speaking, the corresponding bit should be set when and only when the error happens. 

8.1.3.3.6 Memory Error Detection
EVE supports parity-based error detection for all internal data memories (including DMEM, WBUF,
IBUFLA, IBUFLB, IBUFHA, and IBUFHB) on the minimum access size granularity of 8 bits (that is, there is
1 bit of parity per byte of memory). EVE subsystem also implements double bit error detection for program
cache SRAM through a distance 3, 10-bit Hamming code. The 10-bit Hamming code is also applied to the
tag and address for a particular cache line.
When parity is enabled, write accesses to any memory cause the parity/encoding bit(s) to be calculated
for the specific write data (along with tag and address value for program cache) and written to the
corresponding encoding location. For all read accesses from any data memory, the parity bit is read and
compared against previously calculated parity for the current pattern in the memory. For program cache,
only ARP32 program fetches perform stored versus expected encoding comparison (accesses through
program cache OCP debug target port do not result in code calculation). If a mismatch occurs the error
details are recorded in parity error MMR (different for each memory - IBUF, WBUF, DMEM) and the
associated interrupt is asserted. At the same time, an OCP error response is generated.