Our customer is performing the JEDEC compliance testing for DDR4 and found that DQS is delayed in Read or Write operation. It seems that the start of DQS activity is delayed by about 10nsec from the start of DQ activity.
The following are signal traces in Read or Write operation, yellow for CK, green for DQS1 and blue for DQ11.
It is confirmed that the trace length skew between DQS and DQ is less than 2psec.
Linux is used with the same settings as in the compliance testing, but it is working fine and the DDRPHY_PGSR0 register value confirmed in U-Boot is 0x80004FFF which indicates that the DDR4 initialization was completed successfully.
Could you guess why DQS is delayed?
Best regards,
Daisuke
