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We only can find the CSPW2G block diagram from the DRU821U TRM page : 5723.
See below picture posted.
So, where is the CPSW5G/9G from the TDA4 TRM? please specify.
Some customers are asking what's the difference between those 3, they know the speeds are diff.
But, what about the Block diagram diff between those 3?
BR Rio
Hi,
>So, where is the CPSW5G/9G from the TDA4 TRM? please specify.
You can see the block diagram under "High Speed Serial Interfaces -> Gigabit Ethernet Switch (CPSW0) -> CPSW0 Functional Description". Right now due to an error in J721E TRM it shows for CPSW 5G instead of CPSW 9G but I am attaching the correct diagram for CPSW 9G below
> Some customers are asking what's the difference between those 3, they know the speeds are diff.
I don't think there's a single page or presentation which explains the difference. CPSW 5G/9G are pretty much identical except for number of ports. CPSW 2G is an older IP.
> But, what about the Block diagram diff between those 3?
I am sorry but there is no documentation which compares them with each other. We only have descriptive documentation under the TRM. This is something that I will take under as suggestion and work on for future SDK releases.
Regards
Vineet
Hi Vineet:
Do you have some NDA slides or something we can show to the customers?
Since TDA4 / DRA8 have so much chip versions, customers need this kind of detail information to know the diff.
This is because they need to check the BOM Cost (price) vs the CPSW performance.
please help.
BR Rio
Hi Rio,
Let's discuss this offline. Please accept the answer above if nothing else.
Regards
Vineet