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AM3352: GPMC NAND timing configuration: WRACESSTIME, RDACCESSTIME

Tony Tang
Mastermind 30632 points

Part Number: AM3352

Did not find a timing figure depict what is WRACCESSTIME, even in the NAND Data Write Cycle timing figure.

Should config WRACCESSTIME end at WEOFFTIME?

While in NAND Data Read cycle timing figure has RDACCESSTIME. BTW, should config OEOFFTIME=RDACCESSTIME?

also did not find WRACCESSTIME and RDACCESSTIME in datasheet Table 7-30 GPMC and NAND Flash Switching Characteristics.

  • 0
    TI__Mastermind 30631 points

    Hi Tony,

    Tony Tang said:
    Should config WRACCESSTIME end at WEOFFTIME?

    The WRACCESSTIME parameter doesn't really matter for NAND. The command/address/data is on the A/D bus from the beginning of the cycle through the entire cycle.
    During writes, WRACCESSTIME allows for the capture of the WAIT signal. Since the WAIT pin is NOT monitored during a NAND command/address/write cycle, the WRACCESSTIME does NOT need to be set to a value 2 cycles after WAIT pin is guaranteed to be valid.

    In asynchronous write mode, the GPMC_CONFIG6_i[[28-24] WRACCESSTIME timing parameter is not used to define the effective write access time. Instead, it is used as a WAIT invalid timing window, and must be set to a correct value so that the gpmc_wait pin is at a valid state two GPMC_CLK cycles before WRACCESSTIME completes.
    Refer to AM335x TRM (SPRUH73Q) section 7.1.2.3.9.8.2 Access Time on Write Access.

    For NAND configuration it is specified that GPMC_CONFIG1_i [WAITWRITEMONITORING] = 0, Wait not monitored by GPMC access engine.
    Refer to TRM section 7.1.2.3.12.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode

    Tony Tang said:
    should config OEOFFTIME=RDACCESSTIME?

    RDACCESSTIME should be set after OEn/REn rising edge (OEOFFTIME) to allow for data propagation delay from REn rising edge.
    Refer to 7.1.2.3.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode

    The ready/busy signal from the NAND is polled through the register
    GPMC_STATUS or GPMC_IRQSTATUS during NAND start-up/initialization sequence.

    During regular NAND operation, software should read ready/busy status from the READ STATUS (70h) command (bit 5) or poll/interrupt on GPMC_STATUS or GPMC_IRQSTATUS registers.
    The wait pin is not used during the command, address, data cycles of NAND protocol.

    Regards,
    Mark