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AM6442: IPC example codes

Part Number: AM6442


Hi everyone,

I try ipc rpmcg echo linux example code which runs on r5f0_0 core and sends messages to a53. But on the Linux terminal (a53), I cannot see any result. Also, I try ipc notify echo code which runs on r5f0_0 and sends messages to other r5f cores. The sample result shown in the explanation of the example project does not show up in my case. I am running Processor-SDK-Linux-AM64x on a53 and FreeRTOS on r5f.

When I connect r5f0_0 core, the console shows the below message:

MAIN_Cortex_R5_0_0: GEL Output: Running from R5
MAIN_Cortex_R5_0_0: GEL Output:

DDR not initialized with R5 connect.

Go to menu Scripts --> AM64 DDR Initialization -> AM64_DDR_Initialization_ECC_Disabled to initialize DDR.   (1)

When I try to do (1),  I get the following messages:

MAIN_Cortex_R5_0_0: GEL Output: --->>> ECC Disabled <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR controller programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 0 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 1 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address slice 2 programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY Address Slice 2 programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> Set PHY registers for all FSPs simultaneously (multicast)... <<<---
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PHY programming completed... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Setting MAIN_PLL12_HSDIV0_CLKOUT_400MHz
MAIN_Cortex_R5_0_0: GEL Output: MAIN_PLL12_HSDIV0_CLKOUT set.
MAIN_Cortex_R5_0_0: GEL Output: Setting DDR4 frequency...
MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from PI...
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR PI initialization started... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Triggering start bit from CTL...
MAIN_Cortex_R5_0_0: GEL Output: --->>> DDR CTL initialization started... <<<---
MAIN_Cortex_R5_0_0: GEL Output: Polling PI DONE bit...
MAIN_Cortex_R5_0_0: GEL Output: pi_int_status = 0x29C12003...
MAIN_Cortex_R5_0_0: GEL Output: - PI_INIT_DONE_BIT set: The power-on initialization training in PI has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_CA_PARITY_ERR_BIT set: A parity error has been detected on the address/control bus
MAIN_Cortex_R5_0_0: GEL Output: - PI_LVL_DONE_BIT set: The leveling operation has completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_DLL_LOCK_STATE_CHANGE_BIT set: A state change has been detected on the dfi_init_complete signal after initialization.
MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_GATE_DONE_BIT set: A read leveling gate training operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_RDLVL_DONE_BIT set: A read leveling operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_WRLVL_DONE_BIT set: A write leveling operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - PI_VREF_DONE_BIT set: A VREF setting operation has been completed.
MAIN_Cortex_R5_0_0: GEL Output: - Not documented bit set.
MAIN_Cortex_R5_0_0: GEL Output: ctl_int_status = 0x00000008...

At this point (MAIN_Cortex_R5_0_0: GEL Output: ctl_int_status = 0x00000008...), process does not stop.

Could anyone help me figure out this problem?

Details of the Linux SDK:

Version: 07.03.01.006
Release date: 30 May 2021
Details of the MCU SDK:
Version: 07.03.00.19
Release date: 09 Apr 2021
Thanks in advance,
Ravan.
  • Hi Ravan,

    Some questions:

    • Is Linux running on the A53s when trying this? Do you observe this behavior without Linux running? 
    • What boot mode is your EVM in? Boot modes are shown here: EVM Setup
    • When you connect your EVM to a UART terminal, what do you see after a power-cycle?

    Regards,
    Sahin

  • Hi Sahin,

    Thanks for your kind reply.

    -> Yes, Linux SDK is running on A53 when I try the example code. I also tried ipc notify echo code which runs on r5f0_0 and sends messages to other r5f cores. This example has nothing to do with Linux.  It either doesn't give the expected results shown in he following page: https://dev.ti.com/tirex/explore/node?node=AH-DaDw6WiduEahUDgLr3A__rN4Qml4__LATEST

    ->I boot from SD card which has wic file for Linux SDK.

    ->After connecting EVM to UART terminal, the Linux is booting and the emulator program show Arago Project:

    (similar to the picture below)

    Thanks,

    Ravan.

  • I suspect you are unable to connect to the R5F's via CCS because Linux is running on the A53s and Linux typically takes control of the system. I would also expect Linux to initialize the DDR already which would explain why the CCS DDR initialization is failing.

    If you remove the SD card and power-cycle the board so that Linux isn't running, you should be able to run the CCS DDR initialization and connect to the R5Fs (after doing the SOC initialization described here: EVM SETUP - you can either flash the SOC initialization binary or do the CCS scripting method using load_dmsc.js) and then you should be able to load and run the R5F <-> R5F IPC example. 

    I'm looping in the Linux experts to confirm and comment further on the Linux A53 IPC example.

    Regards,
    Sahin