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EVMK2G: Configuring timers and interrupts by means of CSL APIs: ISR executed only the first time!

Benito Carotenuto
Intellectual 366 points

Part Number: EVMK2G

Hi experts.

for my work I have to program the EVMK2G in order to execute a task at fixed time by means of  DSP C66x.

I read the paper "Configuring Interrupt on Keystone Device" and I focused on the section "Using CSL APIs".

This is exactly what I would like to do! I want to trigger the task ISR when TIMER2_LO matches its period . 

I downloaded pdk_k2g_1_0_16 and I installed CCS10.2.

I developed a code taking a cue from the example C:\ti_hpc\pdk_k2g_1_0_16\packages\ti\csl\example\timer_test.c. However it does not work.

Specifically, the interrupt is executed only 1 time, although I set the TIMER2 in dual 32bit unchained continuous mode and I selected  eventID=CSL_C66X_COREPAC_TIMER_2_INTL.

I noticed the following behaviour:

  1) as the timer starts,  the register TIMER_INTCTL_STAT.PRDINTSTAT_LO is set to 1  (despite the counter has not yet matched the period value);

  2) consequently, the register IFR is set to 1; 

  3) as the counter matches the period value, the ISR is executed;

  4) both the registers IFR and TIMER_INTCTL_STAT.PRDINTSTAT_LO are permanently set to 1  

  5) the timer continues to count but no interrupt is generated.

How should I clear the IFR and the TIMER_INTCTL_STAT.PRDINTSTAT_LO? Is this the reason for which no interrupt propagates after the first one?

I read several post and I realized that other users had the same problem.

I also tested the pdk_k2g_1_0_16\packages\ti\csl\example\timer\timer_test.c but the problem remains.

I attach my workspace project.

 workspace_timer.zip

Thank you in advance.

Best regards,

Benito

  • 0
    TI__Expert 8885 points

    Hi Benito,

    There is a unit test for timer under K2G OSAL component. This test gets the periodic timer interrupts (like 100 in the test) and passes.

    I think, it may be CSL example issue. While I take a look on the CSL example on what could be wrong, can you please try the OSAL unit test and note timer unit tests are good at your side?

    Thanks

  • 0 in reply to Aravind Batni
    Intellectual 366 points

    Dear mr. Aravind Batni,

    thank you for your availability. 

    Do you refer to C:\ti_hpc\pdk_k2g_1_0_16\packages\ti\osal\test\src\main_osal_test.c ?

    I have found a test concerning timer within this file.

    Kind regards,

    Benito

  • +1 in reply to Benito Carotenuto
    TI__Expert 8885 points

    Hi Benito,

    Yes, that is the one. There are other tests as well, but you can focus on timer test.

    I noticed that the osal test is not enabled for evmK2G.. From the release it is enabled only for iceK2G board. You would need to enable the test for evmK2G as well. Please follow Step #2 as shown below to enable it for evmK2G.

    The way to build it is:

    1. <pdk>\packages\ pdksetupenv.bat

    2.  Add evmK2G to libosal_BOARDLIST variable defined under <pdk>\packages\ti\osal\osal_component.mk file

    libosal_BOARDLIST       = evmAM572x evmAM335x evmAM437x iceK2G idkAM574x idkAM572x idkAM571x idkAM437x am65xx_evm am65xx_idk evmOMAPL137 lcdkOMAPL138 evmK2E evmK2H evmK2K evmK2L j721e_evm j7200_evm tpr12_evm evmK2G

    3. cd <pdk>\packages\ti\osal\ gmake

    After Step #3 completes, you will get the executables under <pdk>/packages/ti/binary folder.

    Load the appropriate OSAL test one for the board that you are using.

    Note that the tests output to UART console, so you need to connect to appropriate serial port to observe the output.

    I am attaching the UART output as well here, for your reference. As you can see in the test, 100 timer interrupts are fired (Test stops after 100 interrupts). You can refer to OSAL_timer_test() in the c file and you can use the OSAL timer API (which is built on top of CSL APIs for baremetal timer support).

  • 0 in reply to Aravind Batni
    Intellectual 366 points

    Dear mr. Aravind Batni,

    thank you for your availability. 

    I successfully performed the OSAL_timer_test on the board EVMK2G. 

    Now, I am dealing with the porting of this code within my project. In order to do this, I need to deeply study it. As I told you, for my work I need to implement a task at fixed time.

    May I complete the porting before to mark this post as resolved in order to have the opportunity to add a further question?

    Thank you for your kindness.

    Best regards,

    Benito Carotenuto

    PS. Are any news about the reason for which the test pdk_k2g_1_0_16\packages\ti\csl\example\timer\timer_test.c  within my workspace does not work? I read several posts concerning problems with the implementation of interrupt by means of CSL APIs but no solution has been provided.

     

  • +1 in reply to Benito Carotenuto
    TI__Expert 8885 points

    Hi Benito,

    When I took a look on the csl example for the timer, I noticed that the example is not ported/supported to k2g. 

    snippet from csl_component.mk under ti/csl folder:

    csl_timer_app_BOARDLIST = tda2xx-evm tda2px-evm tda2ex-evm tda3xx-evm idkAM572x idkAM571x evmAM572x evmDRA72x evmDRA75x evmDRA78x tda2xx-rvp idkAM574x

    As you can see, it does not contain any K2G boards, which indicates that the example is not supported for none of the K2G boards. It would need some porting effort to make it functional on K2G. Also, please note that the  timer IP in K2G is different than the SoCs that are mentioned above. So, the CSL timer example does not work for K2G.

    As you can see, the CSL APIs are good to be used for timer, which is abstracted in OSAL APIs to support ease of use. If you go with OSAL APIs for Timer, probably, it would save some time for you. Do you see any issues/bottleneck on using  the OSAL APIs for timer?.

    I see you mentioning about running a task on a periodic basis. Note that the "CSL/OSAL" non -os examples are written for Single Task environment.

    I am wondering if you can use TI-RTOS for multi task application. Note that the OSAL Timer APIs are common between Baremetal and TI-RTOS.

    FYI: The baremetal OSAL timer API implementation is built on top of CSL and TI-RTOS implementation is built on top of SYS BIOS.

    I think w.r.t. to this thread, you may be able to resolve the thread (timer interrupts are not limited to only one time) and possibly open a new one for next questions.

    Thanks