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EDMA3 GPIO Synchronization in OMAP-L138

1258021
Genius 5120 points
Other Parts Discussed in Thread: OMAP-L138

Hi,

We wanted to use the one of the GPIO from the OMAP-L138 as Synchronization event for EDMA3.

In SPRS586B_2010_AUG_OMAL-138_Low_Power_Application_Processor, page number - 112 says that the event number related to the GPIO Bank-0 Interrupt is 6.

I am using one of the GPIO Bank - 0 pin (GPIO[0][1]) as synchronization for transfer with EDMA3 and another peripheral is connected to the (GPIO[0][2]). I want to interrupt the processor with GPIO[0][2] pin also.

If my understanding is correct since GPIO[0][1] and GPIO[0][2] both generate the GPIO Bank-0 Interrupt EDMA tranfer is submitted in both the cases to Transfer Controller of the EDMA3.

Or Is there any register which we can configure so that the transfer is submitted to Transfer Controller only when GPIO Bank-0 Interrupt occurs.

Please advise on this and thank you for reading the post.

Regards,

GSR

  • 0
    TI__Genius 14545 points

    GSR,

    1258021 said:
    Is there any register which we can configure so that the transfer is submitted to Transfer Controller only when GPIO Bank-0 Interrupt occurs.

        You are correct in that the GPIO module will present an system event that will be mapped to both a interrupt controller as well as the EDMA3. If there is a single event from the GPIO bank, there isn't a way only alert either the EDMA3 -or- the Interrupt Controller independently.

    Both the EDMA3 Channel Controller as well as the Interrupt Controller allow you to mask off events (same concept as an Interrupt Enable Mask). By doing this you effectively disable an interrupt from GPIO[0][1] from causing a EDMA3 transfer, or GPIO[0][1] from causing a interrupt - however this assumes you have full knowledge about the interrupt order, timing, etc. and also requires you to perform a the masking/unmasking in software.

     

    If you don't have control, you have some more additional options to explore

    [1] Use an Interrupt Service Routine in the CPU to poll which GPIO caused the interrupt event , and in the case of GPIO[0][1] you can manually trigger a EDMA3 Event using either a DMA or a QDMA channel.

    [2] Use the EDMA3 to handle both GPIO events, but utilize the Transfer Completion Code Interrupt from the EDMA3 (along with a Dummy Transfer) to handle GPIO[0][2]. This way the EDMA3 will provide an interrupt to the CPU when the transfer is complete in which you can store the ISR for GPIO[0][2].

    I'm sure there are other ways of doing this as well, but I just wanted to provide you with a few options.

     

     

  • 0 in reply to dabuan
    Genius 5120 points

    Hi Drew Abuan,

    Thank you for the reply.

    Regards,

    GSR

  • 0 in reply to dabuan
    Expert 1275 points

    dabuan said:
    Both the EDMA3 Channel Controller as well as the Interrupt Controller allow you to mask off events (same concept as an Interrupt Enable Mask). By doing this you effectively disable an interrupt from GPIO[0][1] from causing a EDMA3 transfer, or GPIO[0][1] from causing a interrupt - however this assumes you have full knowledge about the interrupt order, timing, etc. and also requires you to perform a the masking/unmasking in software.

    I dug into the datasheets for the OMAP L138, but I could not find any GPIO mask register for the EDMA controller. Which register controls the GPIO to event mapping?

    I want one GPIO pin to generate a EDMA event. The other GPIO's on that bank should generate interrupts as usual. If i inderstood correctly, this is possible, because the GPIO interrupt mask and the EMDA mask (which I was unable to locate) are two different things.