DRA821U: How to debug with CCS after booting

Daisuke Maeda

Guru 20025 points

Part Number: DRA821U

Our customer wants to debug using CCS after booting from SD card. They used the customized GEL files to read the PLL registers, but the read failed. The GEL files were set up by following the procedure linked below, and ran by connecting DMSC_Cortex_M3_0. The launch.js script was unused because the DMSC firmware has already been executed by booting.

software-dl.ti.com/.../ccs_setup_j7200.html

Attach the customized GEL files here:

J7VCL_SI.gel

J7VCL_PLL.gel

Attach the GEL output log here:

ccs_log1.txt

DMSC_Cortex_M3_0: GEL Output: Debugging disabled.
DMSC_Cortex_M3_0: GEL Output: Reading off all PLLs configuration.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 3 (CPSW5X PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000003
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00003000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 4 (Audio 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000004
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00004000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 7 (MSMC PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000007
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00007000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000008
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00008000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000C
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000C000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000E
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000E000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 1 (MCU Peripheral PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 2 (MCU CPSW PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Reading off all PLLs configuration ...done.

By the way, the SBL test application (sbl_baremetal_boot_test_j7200_evm_mpu1_0TestApp_release) is used as the MPU application.

software-dl.ti.com/.../boot_k3.html

The thread related to this post is here: e2e.ti.com/.../dra821u-how-to-change-the-initial-mpu-a72-clock-frequency-in-sbl

Best regards,

Daisuke

over 3 years ago

0 Daisuke Maeda over 3 years ago

Guru 20025 points

Hi,

Our customer tried to debug by connecting DMSC_Cortex_M3_0 after launching the CCS debugger.

Are their steps correct for debugging the target after booting?

If not, does the launch.js script need to be used?

The customized GEL file was run by connecting DMSC_Cortex_M3_0 and read the PLL registers, but the values of all fields showed 0. Please check OnTargetConnect() in J7VCL_SI.gel and Get_All_PLL () in J7VCL_PLL.gel for reading the PLL registers.

Are there any failures in the customized GEL file?

Is any other step required to read the PLL register?

Please give me an answer as soon as possible. Your prompt reply would be appreciated.

Best regards,

Daisuke

0 Karan Saxena over 3 years ago in reply to Daisuke Maeda

TI__Guru* 76613 points

Hi Daisuke,

If you have booted the board using some bootloader (SPL or SBL) then there is no need to run the launch.js or the GEL files to debug.

Are you trying to read some MMR registers which could be protected by a lock?

Regards,

Karan

0 Daisuke Maeda over 3 years ago in reply to Karan Saxena

Guru 20025 points

Hi Karan-san,

Thank you for your reply.

Is it required to be unlocked by the Kick Protection Registers before the PLL registers are read?

I understand that the protection mechanism for registers only prevents writes.

Best regards,

Daisuke

0 Daisuke Maeda over 3 years ago in reply to Karan Saxena

Guru 20025 points

Hi Karan-san,

We added an unlock by the Kick Protection Registers before reading the PLL registers in the GEL file, but all read values still show 0.

Attach the customized GEL files here:

0741.J7VCL_SI.gel

8203.J7VCL_PLL.gel

Attach the GEL output log here:

1541.ccs_log.txt

DMSC_Cortex_M3_0: GEL Output: Debugging disabled.
DMSC_Cortex_M3_0: GEL Output: Reading off all PLLs configuration.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 0 (Main PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80680008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80680038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80680030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80680034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 1 (Peripheral 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80681008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80681038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80681030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80681034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 2 (Peripheral 1 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80682008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80682038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80682030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80682034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 3 (CPSW5X PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000003
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00003000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80683008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80683038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80683030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80683034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 4 (Audio 0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000004
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00004000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80684008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80684038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80684030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80684034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 7 (MSMC PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000007
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00007000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80687008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80687038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80687030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80687034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 8 (ARM0 PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000008
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00008000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x80688008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x80688038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x80688030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x80688034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 12 (DDR PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000C
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000C000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x8068C008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x8068C038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x8068C030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x8068C034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off Main PLL 14 (Main Domain Pulsar) PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x00680000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x0000000E
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x0000E000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x8068E008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x8068E038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x8068E030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x8068E034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 0 (MCU PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000000
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00000000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x60D00008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x60D00038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x60D00030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x60D00034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 1 (MCU Peripheral PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000001
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00001000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x60D01008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x60D01038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x60D01030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x60D01034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Read off MCU PLL 2 (MCU CPSW PLL)
DMSC_Cortex_M3_0: GEL Output: Base address: 0x40D00000
DMSC_Cortex_M3_0: GEL Output: PLL index: 0x00000002
DMSC_Cortex_M3_0: GEL Output: PLL index register base: 0x00002000
DMSC_Cortex_M3_0: GEL Output: Register: 0x00000020
DMSC_Cortex_M3_0: GEL Output: PLL_CONFIG register address: 0x0x60D02008
DMSC_Cortex_M3_0: GEL Output: OUTPUT_DIV_CONTROL register address: 0x0x60D02038
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_0 register address: 0x0x60D02030
DMSC_Cortex_M3_0: GEL Output: FREQ_CONTROL_1 register address: 0x0x60D02034
DMSC_Cortex_M3_0: GEL Output: Reference Divider is:     0
DMSC_Cortex_M3_0: GEL Output: Feedback Divider is:      0
DMSC_Cortex_M3_0: GEL Output: Fractional Multiplier is: 0
DMSC_Cortex_M3_0: GEL Output: Output Divider #1 is:     0
DMSC_Cortex_M3_0: GEL Output: Output Divider #2 is:     0
DMSC_Cortex_M3_0: GEL Output: Number of hsidvs: 0
DMSC_Cortex_M3_0: GEL Output: Parsed PLL configuration information.
DMSC_Cortex_M3_0: GEL Output: Reading off all PLLs configuration ...done.

Please check OnTargetConnect() in J7VCL_SI.gel and Get_All_PLL () in J7VCL_PLL.gel for reading the PLL registers.

Is any other step required to read the PLL register?

Best regards,

Daisuke

0 Daisuke Maeda over 3 years ago in reply to Karan Saxena

Guru 20025 points

Hi Karan-san,

Post additional information.

Our customer used the memory browser view on CCS to check the PLL registers.

The values read by DMSC_Cortex_M3_0 showed 0.

CortexA72_0_0 or MCU_Cortex_R5_0 succeeded in reading the values.

Best regards,

Daisuke

0 Karan Saxena over 3 years ago in reply to Daisuke Maeda

TI__Guru* 76613 points

Hi Daisuke-san,

Let me try to replicate this and get back to you.

Regards,

Karan

0 Karan Saxena over 3 years ago in reply to Karan Saxena

TI__Guru* 76613 points

Hi Daisuke-san,

I see the address 0x688030 for PLL0_CFG_PLL8_FREQ_CTRL0 in TRM, how do you get the address 0x80688030 which you are checking from M3? I have also notified the HW team on this question.

Regards,

Karan

0 Daisuke Maeda over 3 years ago in reply to Karan Saxena

Guru 20025 points

Hi Karan-san,

Thank you for your reply.

I referenced the default GEL file for the address 0x80688030. The default GEL file (J7VCL_PLL.gel) uses the address offset 0x80000000 in Set_All_PLL().

The values read by DMSC_Cortex_M3_0 with the address 0x688030 also showed 0.

Best regards,

Daisuke

0 Parth Nagpal over 3 years ago in reply to Daisuke Maeda

TI__Mastermind 42135 points

Hi Daisuke-san,

I tried to replicate the issue on my setup. I booted the board with SD card and connected to DMSC_Cortex_M3_0 with the default gel files. I am able to read the PLL registers from the memory browser. Looks like there is some issue with the customized gel files that you are using. Could you please try with the default gel files and see if you are still facing the issue.

Also, is there a specific reason to use M3 for debugging and not the R5 or A72 directly?

0 Daisuke Maeda over 3 years ago in reply to Parth Nagpal

Guru 20025 points

Hi Parth Nagpal-san,

Thank you for your reply.

Our customer has achieved their goal by reading the PLL registers with R5 or A72 after booting.

Initially, we tried to use the script "Get_PLL_Configuration()" for reading the PLL registers that is provided in the default GEL file "J7VCL_PLL.gel".

I am wondering why DMSC_Cortex_M3_0 cannot read the PLL registers, but I understand that DMSC_Cortex_M3_0 cannot be used to debug using CCS.

Best regards,

Daisuke

+1 Parth Nagpal over 3 years ago in reply to Daisuke Maeda

TI__Mastermind 42135 points

Hi Daisuke-san,

We are glad to hear that your customer has achieved their goal. DMSC_Cortex_M3_0 can be used to read the registers but it is not ideal for debugging as it restricts access to some memory space.
If you have no further questions, please click on verify answer.

Regards,

Parth Nagpal

0 Daisuke Maeda over 3 years ago in reply to Parth Nagpal

Guru 20025 points

Hi Parth Nagpal-san,

Thank you for your reply.

Best regards,

Daisuke

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