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AM3358: Configure PHY CLKOUT before PRU FW start

Part Number: AM3358


I am working on a custom board based on AM3358 and running Linux RT (sdk-linux-rt-am335x-evm-06.03.00.106)

The hardware design includes 2 PHY where one is sharing REF_CLK with the other via CLKOUT pin.

To enable the CLKOUT pin to share REF_CLK I would expect Linux being able to write PHY registers via PRU-ICSS MDIO bus (pruss_mdio: mdio@4a332400).

&pruss_mdio {
    pinctrl-0 = <&pruss_mdio_default>;
    pinctrl-names = "default";
    status = "okay";

    pruss_eth0_phy: ethernet-phy@2 {
         reg = <2>; /* TJA responds to PHY address 0 */
         reset-gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
         reset-assert-us = <20>; /* PHY datasheet states 5 uS min - 20 us max */
         reset-deassert-us = <100>; /* Wake-up time */
    };

    pruss_eth1_phy: ethernet-phy@3 {
         reg = <3>;
         reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
    };
};

My questions are:

  1. how can I register a phy fixup for my particular PHY device in order to write the proper register configuration to share CLKOUT (the 2 phy devices have different PHY-IDs from different vendors) ?
  2. is the pruss.c driver able to configure PHYs before PRU FW being started ?
  3. how to prevent PRU FW to reset PHY devices ?

Thank you in advance

   Andrea

  • Hello Andrea,

    1) Are you using a specific protocol on the PRUs? If so, which ones?

    2) I am not sure I understand your third question. Please give more details about "how to prevent PRU FW to reset PHY devices"

    Regards,

    Nick

  • Hi Nick,

          I am just running on PRUs the default FW taken from SDK (sdk-linux-rt-am335x-evm-06.03.00.106).

    About point 3) I am wondering if PRU FW will reset MDIO bus and PHY devices at startup.

    In such case PHY configuration applied by Linux will be erased.

    Thanks

       Andrea

  • Hello Andrea,

    The PRU firmware does not reset the MDIO bus and PHY devices. My understanding is that the PHY configures itself based on resistor settings as soon as it is powered. However, the value of AM335x pins connected to the PHY resistors is not guaranteed before those pins are initialized. That means that the PHY might be in a bad state. So the prueth driver should use the reset-gpio argument you pass in the device tree to reset the PHY as it is setting up the PRU Ethernet. That ensures that the AM335x pins are at a known value, which ensures that the PHY is in a good state when the MDIO driver tries to communicate with it.

    Why are you trying to use the same clock for both PHYs? Why not have decoupled clocks?

    Please share a snippet of your schematic showing how you have the PHYs connected.

    Regards,

    Nick