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AM6412: General Questions

RJ
Intellectual 2550 points
Part Number: AM6412
Other Parts Discussed in Thread: AM6442, , PROFIBUS, LP8733, SYSCONFIG

Hi Team,

I noticed that TI come out AM64x series Sitara chip, I just ordered start kit of it for evaluation purpose. Currently I am thinking of using AM6412 (dual-core A53 with single core R5F), I knew that AM6412 would be released on Q4 of 2021, so I guess I probably have to use AM6442 on my prototype board.

I got a couple questions here,

1, do you have a single PMIC chip solution suggested for power up AM64x chip? I looked at the start kit schematic, looks like there are more than 3 chips, and there are power up and power down sequence specified also. What would be happen when lost power and unit doesn’t go through power down sequence, is it going to introduce latch-up condition to the chip?

2, for the cortex R5F core, does it support single precision floating point or double precision floating point?

3, for AM6412, in datasheet, feature of “industrical communication subsystem support” is marked as “No”, I guess it means not support for “profibus”, “ethercat” …, how come? Is the PRU different between AM6412 and AM6442? Is the PRU in AM6412 has less RAM comparing with AM6442?

4, on datasheet, it specified that “USB3.1 and PCIe share a common SerDes lanes”, what is imply? Is it meaning that USB3.1 and PCIe cannot work simultaneously at the same time? Would you please elaborate what’s the impact of this “share a common SerDes lanes”? USB and PCIe can work at the same time, but share the same throughput bandwidth limited by this SerDes lane, maybe?

  • 0
    TI__Guru**** 169071 points

    Hi Ramon,

    I will let other experts answer your question 1-3, but I can take #4:

    This implies USB super-speed and PCIe cannot be used simultaneously.

    The SerDes is the PHY taking care of the Gbps transfers, so PCIe would require SerDes to function. But the USB module also has a USB2.0 PHY to support USB high-, full-, and low-speed. So you would have the following usecases:

    - PCIe + USB 2.0, or

    - USB 3.1 with no PCIe

  • 0 in reply to Bin Liu
    TI__Guru* 87040 points

    There is no single PMIC at this time.  The SK is the best example of the most optimized power solution with the LP8733 handling most of the processor voltage rails and their power up sequencing.

    The R5F core supports full precision VFPv3, which has 32 64bit FPU registers  

    The AM6412 does not include the PRU-ICSSG.  It is an optimized variant of the device for customers who do not need the PRU for industrial protocols or other purposes.  If you need the PRU-ICSSG, you would have to go with one of the other variants

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 120 points

    Hi JJD:

        We can see the datasheet，it is say that AM6412 has 2 PRU_ICSSG. like the follow picture. But the "Industrial Communication Subsystem Support" is "No", I want to know detail contain with here "Industrial Communication Subsystem Support" ?

    and detail contain with "Programmable Real-Time Unit Subsystem"?  

  • 0 in reply to Tree ding
    TI__Guru* 87040 points

    Sorry for the confusion, i was incorrect earlier.  The AM641x devices do contain the PRU, but does not include support for ICSSG (industrial protocols).  The PRU can be used as a separate real-time processing unit in the AM641x devices. 

    Regards,

    James 

  • 0 in reply to JJD
    Prodigy 120 points

    Hi JJD：

        Thanks for your answer.

         I want to used AM641x deices to implement industrial general ether gateway, and I will need 5 gigabit ethernet port.

         So I used TI SysConfig tools config 5 gigabit ethernet port (1x CPSW and 4x pru-eth).

         "The AM641x devices do contain the PRU, but does not include support for ICSSG (industrial protocols). "

        Now, Can I used 4x pru-eth for  AM641x devices,?

       I can not find which part is ICSSG and which part is PRU at follow picture "PRU_ICSSG Functional Block Diagram".

  • 0 in reply to Tree ding
    TI__Mastermind 27050 points
    RJ said:
    3, for AM6412, in datasheet, feature of “industrical communication subsystem support” is marked as “No”, I guess it means not support for “profibus”, “ethercat” …, how come? Is the PRU different between AM6412 and AM6442? Is the PRU in AM6412 has less RAM comparing with AM6442?

    and

    Tree ding said:
     I can not find which part is ICSSG and which part is PRU at follow picture "PRU_ICSSG Functional Block Diagram".

    For protocols, networking, ICSS and PRU support the key is one letter in the part number, not the digits. See datasheet (https://www.ti.com/lit/gpn/am6442 ) table 10-1 and the description of part numbers. The part number in general is:

    aBBBBBBrZfYytPPPQ1

    The letter at location f I have highlighted in red determines the PRU and ICSS capability. The capability is in ascending order of capability. Gigabit is not separately enabled, if networking is there, the gigabit capability is there.

    C means just PRU, no ICSS networking
    D means ICSS-PRU is available and can run the networking firmware
    E means also EtherCAT capability is available
    F means the part will run the certified industrial protocol stacks that are provided by TI

    Note that not all possible permutations exist when combined with for example the core counts. For example the F part numbers always have 2 or more R5 cores.

    The evaluation modules always have the the superset F parts.

      Pekka

  • 0
    TI__Mastermind 27050 points
    RJ said:
    2, for the cortex R5F core, does it support single precision floating point or double precision floating point?

    Yes both single and double precision, see TRM https://www.ti.com/lit/pdf/spruim2 section 1.3.2 Arm Cortex-R5F Processor (R5FSS) and statement "Full-precision Floating Point (VFPv3)". 

    With Cortex R5 this means VFPv3-D16. Further detailed documentation is availble at arm.com for example starting from https://developer.arm.com/documentation/ddi0363/e/fpu-programmer-s-model/about-the-fpu-programmer-s-model/about-the-vfpv3-d16-architecture .