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TDA4VM: PCIe module and On-chip interconnect?

AnBer
Mastermind 31205 points

Part Number: TDA4VM

Team,

Could you please help with the below?

Goal is to configure two PCIe modules to access each other.

In this regard, I’ve noticed that I have a lack in understanding how the interconnect of SoC works in detail. I think I’m missing here the bigger picture.

 Up to now, it was sufficient for me to look at the TRM Memory Map of a specific module of interest, to access it functionality via emulator/processor.

For example, GPIO0 module of main domain:

Now I am confronted with a more complex PCIe module:

 There are now some new terms for me, which I am not sure how they fit into “the bigger picture”:

 Q1: What exactly is the CBASS?

Q2: What is VBUS(M/P)?  How does it correlate to CBASS?

Q3: Why has the PCIe module internal AXI ports (marked with (1) ) ?

Q4: If CBASS, VBUS(M/P) and AXI are different busses, do they use different addresses to access the same peripheral (marked with (2))?

Q5: Given the memory map for PCIE0_DAT0: Is this address a CBASS, VBUS(M/P) or AXI address?

Q6: What is the “AXI Stream” (marked with (3))?

Thanks in advance!

  • 0
    TI__Intellectual 2570 points

    Q1: CBASS is Central Bus Architecture SubSystem. CBA is TI proprietary interconnection architecture. Think of it as a TI version of AMBA (ARM interconnect architecture).

    Q2: VBUS(M/P) are Virtual BUS protocol. VBUSP supports single issue, strong in order transfer. VBUSM supports multiple issue, non-blocking, out-of-order transfer to be very simplified. 

    Q3: PCIe internal bus is ARM based AXI inter connect, this is from the IP vendor. 

    Q4: They are different protocols but use same address to access same peripherals. There are protocol conversion bridge to do the "translation" of all metadata. 

    Q5: Same for all.

    Q6: AXI stream is a stream of data transfer issued from the AXI port. 

    Thanks,

    Kai