Hi,
I am supposed to set GPMC as Synchronous Read Burst Access like a Figure 7-166. Wait Behavior During a Synchronous Read Burst Access of TRM.
When I see data of GPMC area with memory browser (CCS), how is valid address (=address of D0) determined?
How does address bus line (GPMC_A0~GPMC_A27) operate?
I presume as described below :
in case of 8 words burst access, valid address is selected every eighth address from the beginning of memory browser window.
Is this understanding correct?
Regards.