Hello,
I'm a hardware designer. I have a board with a Xilinx FPGA & DSP TMS320C6474 connected to each other with SRIO.
And , I need to validate the Xilinx SRIO core configuration.
This is partially done using a EVM SRIO example code. This code does a loopback of 4096 bytes. We were able to get those data on the FPGA side. We are now trying to get them back on DSP side. So far unsuccessful.
To keep it simple, we'd like to generate doorbells on FPGA and check these are received on DSP side. We did not activate interrupts so polling is required.
How should I modify my code to check whether the DSP has received a doorbell or not?
/* Create an LSU configuration */
lsu_conf.srcNodeAddr = (Uint32)&src[0]; /* Source address */
lsu_conf.dstNodeAddr.addressHi = 0;
lsu_conf.dstNodeAddr.addressLo = (Uint32)&dst[0]; /* Destination address */
lsu_conf.byteCnt = TRANSFER_SIZE;
lsu_conf.idSize = 1; /* 16 bit device id */
lsu_conf.priority = 2; /* PKT priority is 2 */
lsu_conf.xambs = 0; /* Not an extended
address */
lsu_conf.dstId = LARGE_DEV_ID;
lsu_conf.intrReq = 0; /* No interrupts */
lsu_conf.pktType = SRIO_PKT_TYPE_NWRITE;
/* write with no
response */
lsu_conf.hopCount = 0; /* Valid for
maintainance pkt */
lsu_conf.doorbellInfo = 0; /* Not a doorbell pkt */
lsu_conf.outPortId = 0; /* Tx on Port 0 */
/* Configure the LSU1 and start transmission */
lsu_no = SELECTED_LSU;
CSL_srioLsuSetup (hSrio, &lsu_conf, lsu_no);
How to loop waiting for doorbell?
resp_db.index = 1;
resp_db.data = 0;
do {
CSL_srioGetHwStatus (hSrio, CSL_SRIO_QUERY_DOORBELL_INTR_STAT, &resp_db);
} while(resp_db.data == 0x00);
printf("%d Doorbell received. %d\n",i,resp_db.data);
Thank you for helping me out.
