Hello everyone, I'm working on a PCIe interface of C6678. The interface is linked with FPGA and everything works fine.
The thing is that the PCIe interface is used by multiple cores and I can't control their priority.
For example, if EDMA TC starts memory write (which takes a lot of time), the memory write operations initiated by C66x cores gets really slow.
I want to set the priority of PCIe memory read/write transfers so that some EDMA tranfers can be preempted by others, but PCIESS of C6678 seems to have only one virtual channel and I cannot do that.
What I've tried: Splitting up transfers to small size, Setting QUEPRI in EDMA, etc.
*Transfers can be initiated by C66x cores and EDMA
