DM8148 DCAN peripheral documentation

John,

I have not forgotten about you and I am currently trying to get the correct expert for you.

BR,

Steve

A reminder of the context. I am using a mistral 8148 EVM board and working on a QNX driver for the DCAN peripherals. (600 MHZ)

I have made a lot of progress with the QNX DCAN driver. I believe I have answered the original question about the registers at 0x481ce000. They seem to be the memory for the message buffers when in a debug mode.

I do have many other questions I would like to get answered.

1. In the DCAN CTL register, what are DE1, DE2, and DE3 to be used for?

2. In the DCAN ES register, how can EWarn be cleared once it gets set?

3. In the DCAN ES register, what are the suggested recovery actions if EPass gets set?

4. How can the counters in DCAN ERRC be reset?

5. I tried setting the IF3UPD registers for a message buffer and it did not work as I was hoping. When the bit is not set, I get an interrupt for a received message and the NewDat bit is set so I know there is a new message. When I set the IF3UPD bit, I don't see any indication that a new message has been received. i.e. no interrupt, no NewDat, no INTPND. Does the 8148 have an interrupt for IF3UPD? I can see in the documentation that there are EDMA events for IF1DMA, IF2DMA, and IF3DMA but I am not sure how to make use of EDMA events within QNX. This probably ties into the DE1, DE2, and DE3 bits that I was asking about above.

6. When I use interrupts, it seems like I don't see all the message events that I should. In the interrupt handler, I keep reading the DCAN INT register and responding to each message number that it returns. But I sometimes seem to miss completed transmits and I have to step through all my pending transmissions to see if they are still in progress. If not, then I assume they must be done.

7. What exactly does SWR (SW reset) do?

8. In many places, the documentation says there are 64 message buffers. But the message numbers in all the registers say the numbers go from 1 to 128. How many message buffers are there?

Thanks.

John,

Here are some answers from the experts...

John Pruitt said:

1. In the DCAN CTL register, what are DE1, DE2, and DE3 to be used for?

Enable DMA request line for IFx, in case DMA should be used to transfer data

John Pruitt said:

2. In the DCAN ES register, how can EWarn be cleared once it gets set?

I think this should get cleared when both the error counters are below 96. The increment/decrement rules for the error counters are defined in the CAN standard

John Pruitt said:

3. In the DCAN ES register, what are the suggested recovery actions if EPass gets set?

Depends on the root cause of the errors in the system. The CAN standard says “11.An ’error passive’ node becomes ’error active’ again when both the TRANSMIT ERROR COUNT and the RECEIVE ERROR COUNT are less than or equal to 127.”

John Pruitt said:

4. How can the counters in DCAN ERRC be reset?

They are reset by a DCAN SW Reset (SWR bit).

John Pruitt said:

5. I tried setting the IF3UPD registers for a message buffer and it did not work as I was hoping. When the bit is not set, I get an interrupt for a received message and the NewDat bit is set so I know there is a new message. When I set the IF3UPD bit, I don't see any indication that a new message has been received. i.e. no interrupt, no NewDat, no INTPND. Does the 8148 have an interrupt for IF3UPD? I can see in the documentation that there are EDMA events for IF1DMA, IF2DMA, and IF3DMA but I am not sure how to make use of EDMA events within QNX. This probably ties into the DE1, DE2, and DE3 bits that I was asking about above.

Mapping of interrupts to A8 is below.

52 = DCAN0_INT0
53 = DCAN0_INT1
54 = DCAN0_PARITY

John Pruitt said:

6. When I use interrupts, it seems like I don't see all the message events that I should. In the interrupt handler, I keep reading the DCAN INT register and responding to each message number that it returns. But I sometimes seem to miss completed transmits and I have to step through all my pending transmissions to see if they are still in progress. If not, then I assume they must be done.

Yes

John Pruitt said:

7. What exactly does SWR (SW reset) do?

Resets the HMH, DCAN protocol controller, etc, except DCAN MMR

John Pruitt said:

8. In many places, the documentation says there are 64 message buffers. But the message numbers in all the registers say the numbers go from 1 to 128. How many message buffers are there?

Max 128 buffers, but supported values are 32/64/128

BR,

Steve