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TMS320C6410 SDRAM Interface

Mehdi Tamehi
Intellectual 450 points
Other Parts Discussed in Thread: TMS320C6410

My customer is using the TMS320C6410. It is connected to 2 Micron SDRAM MT48LC16M16A2 to have a 32 bit data bus. The \CE0 (DSP) is connected to the two \CS of SDRAMs. This set up works just fine.

 

They want to expand more RAM. They then connect another pair of  Micron SDRAM MT48LC16M16A2 to have a 32 bit data bus. The \CE1 (DSP) is connected to the two \CS of SDRAMs. It seems like they have some aliasing happening. Anytime they write to the second set of SDRAM, they actually overwrite the content of the first set of SDRAM’s!!!

 

I have been reviewing datasheet. There is no registers to define the memory block to enable the CE0 and CE1. So how do we define the memory block for each CE0 and CE1?

 

The marking on the DSP is:

 

TMS

320C6410ZTS400

CA-87A0L2W

 

Is this DSP affected with the TMS320C6410 errata?

 

http://focus.ti.com/lit/er/sprz219c/sprz219c.pdf

 

Thanks,

  • 0
    TI__Mastermind 41665 points

    MT said:
    I have been reviewing datasheet. There is no registers to define the memory block to enable the CE0 and CE1. So how do we define the memory block for each CE0 and CE1?

    The CE spaces are defined as regions in the internal memory map of the device, CE0 should be active when accessing 0x80000000-0x87FFFFFF and CE1 should be active when accessing 0x90000000-0x97FFFFFF as given on table 2-2 on page 23 of the datasheet.

    For the problem you describe I am suspecting that there may be a hardware problem, where either the CE lines are crossed somehow, or the SDRAMs themselves are not respecting the CE signal for some reason. I would verify that accessing one region or the other only causes one CE line or the other to assert on the board.

    MT said:
    TMS
    320C6410ZTS400
    CA-87A0L2W
     
    Is this DSP affected with the TMS320C6410 errata?
     

    Yes, the top side marking shows this to be a rev 1.1 silicon device, so the 1.1 silicon errata will apply to it.