Other Parts Discussed in Thread: AM4372
Hi
Hi,
I'm have a customed AM4379 board from am437x-gp-evm board. I'm using the AM4379 GPMC to connect to an extern device using Multiplexed Address Data 16-Bit mode and need 17 address lines.
the address 0~15 is from GPMC_AD[0]~AD[15], address 16 should be from GPMC_A[1] according to Table 9-5 in SPRUHL7H-April 2014 technical reference manual, I can get address 0 ~15, but the address 16 is not correct. when write to GPMC upper address, it always remains 0.
The GPMC_A[1] is pin A21 in mode 1, I config the device tree file as:
gpmc_bus_default: gpmc_bus_default
{
pinctrl-single,pins = <
AM4372_IOPAD(0x800, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
AM4372_IOPAD(0x804, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
AM4372_IOPAD(0x808, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
AM4372_IOPAD(0x80c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
AM4372_IOPAD(0x810, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
AM4372_IOPAD(0x814, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
AM4372_IOPAD(0x818, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
AM4372_IOPAD(0x81c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
AM4372_IOPAD(0x820, PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad8 */
AM4372_IOPAD(0x824, PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad9 */
AM4372_IOPAD(0x828, PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad10 */
AM4372_IOPAD(0x82c, PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad11 */
AM4372_IOPAD(0x830, PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad12 */
AM4372_IOPAD(0x834, PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad13 */
AM4372_IOPAD(0x838, PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad14 */
AM4372_IOPAD(0x83c, PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad15 */
AM4372_IOPAD(0x8a4, MUX_MODE1) /*gpmc a16 */
AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
/* AM4372_IOPAD(0x88c, PIN_OUTPUT| MUX_MODE0) */ /* A12:gpmc_clk(mode0),gpmc_wait1(mode2) */
AM4372_IOPAD(0x88c, PIN_INPUT| MUX_MODE2) /* gpmc_wait1.gpmc_wait1 */
AM4372_IOPAD(0x888, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn3 */
AM4372_IOPAD(0x884, PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn2 */
AM4372_IOPAD(0x880, INPUT_EN|PIN_OUTPUT_PULLUP | MUX_MODE1) /* B9:gpmc_clk(mode1), gpmc_csn1(mode0)*/
AM4372_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpmc_dir */
>;
};
&gpmc {
/*
* When enabling GPMC, disable eMMC and set
* SelEMMCorNAND to output-low
*/
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;/*<&gpmc_bus_default>;*//*<&nand_flash_x8>*/
ranges = <0 0 0x08000000 0x01000000>, /* CS0 space. Min partition = 16MB */
<2 0 0x01000000 0x01000000>, /* CS2 space, FPGA cs2 */
<3 0 0x02000000 0x01000000>; /* CS3 space, FPGA cs3 */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <8>;
gpmc,device-width = <1>;
gpmc,sync-clk-ps = <0>;
/*CONFIG2*/
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <40>;
gpmc,cs-wr-off-ns = <40>;
/*CONFIG3*/
gpmc,adv-on-ns = <0>;
gpmc,adv-rd-off-ns = <25>;
gpmc,adv-wr-off-ns = <25>;
/*CONFIG4*/
gpmc,we-on-ns = <0>;
gpmc,we-off-ns = <20>;
gpmc,oe-on-ns = <3>;
gpmc,oe-off-ns = <30>;
/*CONFIG5*/
gpmc,access-ns = <30>;
gpmc,rd-cycle-ns = <40>;
gpmc,wr-cycle-ns = <40>;
/*CONFIG6*/
gpmc,bus-turnaround-ns = <0>;
gpmc,cycle2cycle-delay-ns = <0>;
gpmc,clk-activation-ns = <0>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
/* MTD partition table */
/* All SPL-* partitions are sized to minimal length
* which can be independently programmable. For
* NAND flash this is equal to size of erase-block */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
partition@2 {
label = "NAND.SPL.backup2";
reg = <0x00080000 0x00040000>;
};
partition@3 {
label = "NAND.SPL.backup3";
reg = <0x000c0000 0x00040000>;
};
partition@4 {
label = "NAND.u-boot-spl-os";
reg = <0x00100000 0x00080000>;
};
partition@5 {
label = "NAND.u-boot";
reg = <0x00180000 0x00100000>;
};
partition@6 {
label = "NAND.u-boot-env";
reg = <0x00280000 0x00040000>;
};
partition@7 {
label = "NAND.u-boot-env.backup1";
reg = <0x002c0000 0x00040000>;
};
partition@8 {
label = "NAND.kernel";
reg = <0x00300000 0x00700000>;
};
partition@9 {
label = "NAND.file-system";
reg = <0x00a00000 0x1f600000>;
};
};
fpga1@1,0 {
compatible = "mtd-ram";//"ti,fram";//cfi-flash";//ti,fram";
linux,mtd-name = "intel,fpga1";
#address-cells = <1>;
#size-cells = <1>;
reg = <2 0 0x01000000>; /* CS2 device IO registers */
bank-width=<2>;
gpmc,sync-clk-ps = <10000>; /*Mininum clock period for synchronous mode, in picoseconds */
/*CONFIG1 */ /*100M:10ns*/
gpmc,mux-add-data=<2>;/*<2>, <1>:AAD-muxed mode(address-address-data mux,A[27:17],A[16:1],D[15:0])
<2>:AD-muxed mode,address-data mux, A[16:1],D[15:0]*/
gpmc,sync-read;/*READTYPE_SYNC */
gpmc,sync-write;/*WRITETYPE_SYNC */
/*gpmc,wait-pin=<1>;*//*wait input pin is WAIT1*/
/*gpmc,wait-on-read;*/
/*gpmc,wait-on-write;*/
/*CONFIG2 */
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <70>;
gpmc,cs-wr-off-ns = <60>;
/*CONFIG3 */
gpmc,adv-on-ns = <10>;
gpmc,adv-rd-off-ns = <20>;
gpmc,adv-wr-off-ns = <20>;
/*CONFIG4 */
gpmc,oe-on-ns = <30>;
gpmc,oe-off-ns = <60>;
gpmc,we-on-ns = <30>;
gpmc,we-off-ns = <50>;
/*CONFIG5 */
gpmc,rd-cycle-ns = <70>;
gpmc,wr-cycle-ns = <60>;
gpmc,access-ns = <60>; /*rd-access-ns */
gpmc,page-burst-access-ns = <10>;
/*CONFIG 6*/
gpmc,bus-turnaround-ns = <10>;
gpmc,cycle2cycle-delay-ns = <10>;
gpmc,wr-data-mux-bus-ns = <20>;
gpmc,wr-access-ns = <40>;
};
fpga2@2,0 {
compatible = "mtd-ram";//"ti,fram";//cfi-flash";//ti,fram";
linux,mtd-name = "intel,fpga2";
#address-cells = <1>;
#size-cells = <1>;
reg = <3 0 0x01000000>; /* CS3 device IO registers */
bank-width=<2>;
gpmc,sync-clk-ps = <10000>; /*Mininum clock period for synchronous mode, in picoseconds */
/*CONFIG1 */ /*100M:10ns*/
gpmc,mux-add-data=<2>;/*<2>*/
gpmc,sync-read;/*READTYPE_SYNC */
gpmc,sync-write;/*WRITETYPE_SYNC */
gpmc,wait-pin=<1>;/*wait input pin is WAIT1*///here must be commented, or fpga2 cann't be probed
gpmc,wait-on-read;
gpmc,wait-on-write;
/*CONFIG2 */
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <70>;
gpmc,cs-wr-off-ns = <60>;
/*CONFIG3 */
gpmc,adv-on-ns = <10>;
gpmc,adv-rd-off-ns = <20>;
gpmc,adv-wr-off-ns = <20>;
/*CONFIG4 */
gpmc,oe-on-ns = <30>;
gpmc,oe-off-ns = <60>;
gpmc,we-on-ns = <30>;
gpmc,we-off-ns = <50>;
/*CONFIG5 */
gpmc,rd-cycle-ns = <70>;
gpmc,wr-cycle-ns = <60>;
gpmc,access-ns = <50>; /*rd-access-ns */
gpmc,page-burst-access-ns = <10>;
/*CONFIG 6*/
gpmc,bus-turnaround-ns = <10>;
gpmc,cycle2cycle-delay-ns = <10>;
gpmc,wr-data-mux-bus-ns = <20>;
gpmc,wr-access-ns = <40>;
};
};
What is wrong? Should there anything I not config to?
Best Regards!
Dudechao
