AM6442: About instruction fetch.

someone will provide a reply early next week. 

tomitama said:

--About SRAM and DDR access routes.--
In SRAM / DDR, is the access route for code fetching the same as the access route for data read / write?
Please tell me the access route of code fetch and data read / write in SRAM and DDR.

See https://developer.arm.com/documentation/ddi0460/d/Functional-Description/About-the-functions for the route inside the R5 core. From the R5 core boundary (AXI master port) the path is shared.

tomitama said:

--About pipeline fetching.--
It is recognized that the R core of AM64 has an 8-step pipeline. Please tell me the timing of instruction fetch.
Is there one instruction to fetch at the same time, and will the next fetch start when the fetch stage ends?
Also, if CBASS conflicts due to fetch and data access, will fetch be delayed as well?

See https://developer.arm.com/documentation/ddi0460/d/Cycle-Timings-and-Interlock-Behavior/About-cycle-timings-and-interlock-behavior/Instruction-execution-overview for a description on the instruction fetch timing on R5. At the AXI master port the R5 accesses for both instruction and data will get serialized. Typically for time sensitive code you would want to use all TCM or instruction cache and and TCM memory for data. You can also consider leveraging the 8-way banking in the SRAM, place instructions in one 256kB region/bank, and data per core in another to avoid conflicts. At DDR all traffic gets serialized again, and should only be used as cached memory to get the advantage of DDR bursts to fill the whole cache line (data or instruction) instead of consuming a burst but only using a word of data.

  Pekka