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EVMK2G: Nested interrupts with the INTC module of the DSP

Benito Carotenuto
Intellectual 366 points

Part Number: EVMK2G
Other Parts Discussed in Thread: OMAPL138

Hi experts,

For my work I am approaching to EVMK2G. My aim is performing a code by means of the DSP (on L2SRAM). 

I downloaded pdk_k2g_1_0_16 and I installed CCS10.2. 

Currently I am configuring the interrupts on the timers by means of the OSAL library (bare metal code).

I configured 3 timers with the following settings:

 - TIMER1: as timer1 expires the function taskISR is executed on interrupt number 14;

 - TIMER2: as timer2 expires the function taskISR2 is executed on interrupt number 13;

 - TIMER3: as timer3 expires the function taskISR3 is executed on interrupt number 15.

All the timers are dual unchained low.

Currently my code works fine because as soon as each timer expires, the corrisponding ISR is executed.

However, I am not able to perform  the nesting of the interrupts.

Specifically, if the taskISR3 is ongoing, the higher proprity tasks (task ISR and taskISR2) are not executed.

Is the INTC module able to manage nested interrupts on the DSP?

 

Thank you in advance for your support.

Best regards,

Benito 

 

  • +1
    TI__Expert 8885 points

    Hi Benito,

    Can you please let me know, if you are trying your application using the Sys Bios OR bare metal (via CSL or OSAL baremetal APIs) from the processor SDK release.

    Thanks

  • 0 in reply to Aravind Batni
    Intellectual 366 points

    Dear mr. Aravind Batni,

    Thank you for your support.

    I use bare metal code.

    Kind regards,

    Benito

    PS. Sorry, I erroneously marked the post as resolved

  • +1 in reply to Benito Carotenuto
    TI__Expert 8885 points

    Hi Benito,

    Sorry for few others question.

    1. Is your application multi task oriented?

    2. Are you building it on top of OSAL TimerP API or directly using the CSL APIs?

    Note that the Processor SDK software for baremetal is validated with single thread (task) with OSAL TimerP APIs and mostly you may need to tweak it for your needs. Also, there are no nested interrupt examples available today.

    From the INTC module on C66x core, it should support nested interrupts.

    Possibly, the similar thread (which was discussed on OMAPL138) may be helpful for you.

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/42231/setting-up-nested-interrupts-on-the-6748-core

    Note the DSP architecture is very much similar (INTC) between them.

    Thanks,
    Aravind

  • 0 in reply to Aravind Batni
    Intellectual 366 points

    Dear mr. Aravind Batni,

    here below the answers to your questions.

    1. Yes, it is a multi task application.

    2. I am building on the top of OSAL TimerP API. I developed the code starting with the OSAL_timer_test() within   C:\ti\pdk_k2g_1_0_16\packages\ti\osal\test\src

    Thank you for your support.

    Regards,

    Benito Carotenuto

  • +1 in reply to Benito Carotenuto
    TI__Expert 8885 points

    Hi Benito,

    Sorry! I may not be able to support multi task application for baremetal, since Processor SDK releases did not have any multi task applications for bare metal.

    I can provide some pointers for you to check/proceed.

    I noticed many places in the OSAL library, there is a global interrupt disable and re-enable during Timer Create/Interrupt handling.

    I think you may need to identify the SW that may be preventing you to get nested interrupts.

    To rule out other issues in your application, possibly, you can create a single task application with 3 timers and see if you are able to handle interrupts from all 3 timers in the single task application.

    You can go through the timer registers and INTC module (Preferably log the register values and check if the Interrupt Flags are set/clear as you expected).

    Thanks

  • 0 in reply to Aravind Batni
    Intellectual 366 points

    Dear mr. Aravind Batni,

    thank you for your support and for your suggestions.

    In my application, ,meanwhile the low priority task (taskISR3) is ongoing, the nesting of the high priority tasks (taskISR and taskISR2) is not allowed because the Global Interrupt Enable (CSR register) is disabled. 

    Consequently, starting from the post you suggested me (https://e2e.ti.com/support/processors-group/processors/f/processors-forum/42231/setting-up-nested-interrupts-on-the-6748-core) I implemented the following additional commands in taskISR3:

    unsigned int old_csr;

    unsigned int old_irp;

    unsigned int old_itsr, old_ier;

    old_irp = IRP ;/* Save IRP */

    old_csr = CSR ;/* Save CSR (and thus PGIE) */

    old_itsr = ITSR; /* Save ITSR */

    old_ier = IER; /* Save IER */

    IER = xxxxx; /* enable INTERRUPT 13 */

    CSR = old_csr | 1 ;/* Enable GIE */

    /* Interrupt service code goes here. */

    /* Interrupts may occur while this code executes */

    CSR = CSR & -2 ;/* Disable interrupts */

    CSR = old_csr ;/* Restore CSR (and thus PGIE) */

    ITSR = old_itsr; /* Restore ITSR */

    IER = old_ier; /* Restore IER */

    IRP = old_irp ;/* Restore IRP */

    Currently, I am able to nest taskISR while taskISR3 is ongoing. 

    I am going to modify the code in order to allow also the nesting of taskISR2.

    Thank you for your support.

    Benito