• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 99 subscribers
  • Views 218 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5718: Changing the sampling timing of WAIT signal in synchronous communication of GPMC

O.H
Mastermind 6430 points
Part Number: AM5718

Hi experts,

Q:Regarding the detection timing of the WAIT signal input to the AM5718, I would like to detect WAIT at an arbitrary timing. Is there such a function? If so, which register should I set?
Example: WAIT signal is detected at the fourth clock after the CS signal is asserted.

The customer is trying to create a board using the AM5718 and connect it to an external device. The external device is a 32-bit RISC CPU, and the customer wants to make adjustments on the AM5718 side to match the specifications of the external device.

I have checked the User's Guide "15.4.4.8.3.1.3 Wait Monitoring During Synchronous Read Access" and "15.4.4.8.3.1.4 Wait Monitoring During Synchronous Write Access". I understood that by changing "WAITMONITORINGTIME", the sampling timing of the WAIT signal can be set to 1 or 2 GPMC_CLK cycles before the original timing(1 GPMC.CLK cycle before the valid data). As a result, I think it is possible to realize WAIT detection at a pseudo-arbitrary timing as long as it is 2 or 3 GPMC_CLK cycles earlier than the valid data. I couldn't understand the explanation in the user's guide, so please let me check it.

Best Regards,
O.H

  • 0
    TI__Expert 6870 points

    Hi,

    Can you explain your use case little bit more? Also, can you mention the SDK, you are using.

    However, as mentioned in TRM -  WAIT signal can be set to 1 or 2 GPMC_CLK cycles before the original timing  and you can configure this through register GPMC_CONFIG1_i[18,19,21,22].

  • 0 in reply to ANUBHAV AKASH
    Mastermind 6430 points

    Hi,

    Sorry for the late reply. Thank you for your answer.

    Currently, they are expecting a problem where they cannot secure enough time (F21=Min2.5ns) between the WAIT signal deasserted timing from the external device (32-bit MCU) and the data reception timing. Refer from "Figure 7-7. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read - (GpmcFCLKDivider = 0)".

    As a countermeasure, they are considering whether it is possible to adjust the WAIT signal detection timing on the AM5718 side, which is why I asked this question. In the past, this timing adjustment was done by FPGA.

    They haven't actually used the SDK yet, and will be evaluating the software. If the problem is not solved by actually adjusting the WAITMONITORINGTIME, please let me check again.

    Best regards,
    O.H