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AM6548: DDR PLL configuration for LPDD4 when using emulator

Milan Oklobdzija32
Intellectual 360 points

Part Number: AM6548
Other Parts Discussed in Thread: SYSBIOS

Hello All,

I have a question regarding clock configuration on AM6548 for LPDDR4 memory rated at 666 MHz when connecting via emulator.
The board in question is our custom board utilizing Micron LPDDR4 memory rated for 666MHz operation. 

My configuration is:
CCS ver: 9.2.0.00013
PDK - pdk_am65xx_1_0_7 (processor_sdk_rtos_am65xx_6_03_00_106)
SYSBIOS - 6.76.3.01

I performed changes in GEL files in order to change PLL3 setting so that clock is set to 333MHz.
In file M4_PLL_Common.gel I replaced settings for DDR4 with existing (but commented out) setting for LPDDR4:


//1333MT/s (666MHz DDR)
#define DDR_M_INT_MULT 480
#define DDR_N_DIV 12-1
#define DDR_M2_DIV 3
#define DDR_SD_DIV 4

PLL3 initalization is correctly done when connecting to the M3 DMSC core.

However, problem is that upon loading DMSC fw DDR PLL is again set to 400MHz.

I tried creating functions in Gel files AM65xEVM.gel and M4_PLL to set PLL3 again to 333MHz before DDR initalization is performed but this is not done correctly (I suppose that SYSFW is preventing this change).

Is there any way to set PLL3 in this case (when using configuration via emulator) without modifying SYSFW?

DDR configuration is already done via TI EMIF tool which was discussed in this post:
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/995930/am6548-am6548-lpddr4-configuration-in-pdk-board-library-gel 

Best regards,
Milan

  • +1
    TI__Expert 6870 points

    Hi,

    It is coming from "sciclient_ccs_init_mcu1_0_release.xer5f" which is loaded from "launch.js". The example is given under "/sciclient/example/sciclient_ccs_init/sciclient_ccs_init_main.c. You can modify the "CSL_DDR_PLL_CLK_FREQ" to your required frequency and build the example, then replace the binary. It will work.

  • 0 in reply to ANUBHAV AKASH
    Intellectual 360 points

    Hello Akash,

    Yes this seems to be the issue. I modified sciclient_ccs_init_main.c and PLL3 clock is correctly set now to 666MHz and I can load and run the code from LPDDR4 now. We will test LPDDR4 extensively now in the following days but it seems to work without problems.
    Many thanks Slight smile

    Best regards,
    Milan