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AM6442: DDR4 timing/simulations

Sam Wilson1
Prodigy 65 points

Part Number: AM6442

Hi,

I am trying to run simulations using IBIS models on the DDR4 interface. To get a more accurate result the simulation software mentioned getting the "pin package lengths" file which will give the length from the die to the pad on the package. This makes timing the interface easier. Will that information ever be available? Also the AM64x DDR Board Design and Layout Guidelines pdf mentions that TI does not provide timing parameters for the processor's DDR PHY interface, will that ever be available either?

Thanks,

Sam

  • 0
    TI__Guru* 95271 points

    Sam, the intention of the appnote is to provide enough design details and requirements to preclude the need for timing analysis.  We don't provide the pin package lengths as those are guaranteed to be length matched.  You only need to length match to the pins of the device when considering the requirements in the appnote.  This IBIS simulations are only needed for SI analysis.

    Regards,

    James 

  • 0 in reply to JJD
    Prodigy 65 points

    Thanks James,

    Are you saying that the pin package lengths are length matched exactly or that they are length matched enough where if you follow the app notes design guidelines that timing will be ok? The app note calls for skew between clock and ADDR_CTRL to be max 3ps. When you account for delays through vias, 3ps is very hard to maintain. The app note mentions vias per trace and via count differences can be exceeded if SI analysis is done. Which is what I'm trying to do, just trying to make sure I get the max amount of detail I can. 

    thanks,

    Sam

  • +1 in reply to Sam Wilson1
    TI__Guru* 95271 points

    Sam, yes they are length matched according to the app note, so you only need to match lengths from the pins of the device.  I would also seek the advice of app note https://www.ti.com/lit/pdf/spraar7 which has more general notes about high speed layout guidelines, especially in the context of vias

    Regards,

    James