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AM5728: GPMC WAIT pin assert time limitation

Kanae
Guru 10085 points
Part Number: AM5728

Hi Support Team,

For the GPMC WAIT pin, the assert time varies depending on the status of peripheral devices.
Is there an upper limit to this assert time?

For example, is it correct that an assert time of about 1us will only cause a delay
in the system operation, but will not break the GPMC access itself?

My customer is assuming TRM: Figure 15-60. Wait Behavior During an Asynchronous Single Read Access.
Please let me know if there are any documents that specify whether or not
there is a limit to the length of the assert time for the wait signal in this behavior.

Best regards,
Kanae

  • 0
    Guru 10085 points


    Hi Support Team,

    Additional information.
    Here is an example of the measured waveform data.
    At this time, it was asserted at a maximum of about 650ns.
    The timescale of the waveform data is 200ns/1div.

    Based on the above, could you please reply to the following questions?


    For the GPMC WAIT pin, the assert time varies depending on the status of peripheral devices.
    Is there an upper limit to this assert time?

    For example, is it correct that an assert time of about 1us will only cause a delay
    in the system operation, but will not break the GPMC access itself?

    Best regards,
    Kanae

  • 0 in reply to Kanae
    Guru 10085 points


    Hi Support Team,

    My customer asserts "wait" intentionally.
    This causes some delay, but this is acceptable for the customer system.

    I would like to know if there is a limit to the assert time in this case.
    Please reply with a schedule of when I can expect a response from your support team.

    If you need other information to reply this thread, please let me know.

    Best regards,
    Kanae

  • 0 in reply to Kanae
    TI__Genius 10180 points

    Kanae,

    Apologies for the delayed response.  GPMC will time out according to the value set in the GPMC_TIMEOUT_CONTROL register.  You could potentially disable the TimeOut feature, but we have known cases mentioned in the TRM (reference NAND Device-Ready Pin) where if you stalled ~50 us, the system may time-out as well.

    Best Regards,

    Shiou Mei

  • 0 in reply to Shiou Mei Huang
    Guru 10085 points

    Hi Shiou,

    Thank you for your support.

    I will share your answer with my customer,
    that the 1 us assert time they are currently experiencing in customer's system
    is not a problem, but as stated in TRM:16.4.4.12.2 NAND Device-Ready Pin,
    problems may occur when the assert time exceeds 50 us.

    Best regards,
    Kanae