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CSL vs SYS BIOS - which to use for cache_wb() and the like

CalvinC
Intellectual 990 points
Other Parts Discussed in Thread: SYSBIOS

We currently use the C6486 CSL API for all cache wb/inv functions. However, I see that the SyS BIOS 6 CACHE module has its own API. Do these conflict? Should I convert to the SYS BIOS API or can I continue to use CSL API for these?

Thanks,

Calvin

  • 0
    Genius 4375 points

    Calvin,  I don't know of anything that would prevent you from continuing to use the CSL cache APIs.  I don't believe there is a conflict.

    However, if you're using IPC it might make sense, from a footprint standpoint, to switch because the SYS/BIOS cache library would get linked into your application due to IPC's dependency on this library.

    Regards,

    Shreyas

  • 0 in reply to Shreyas Oppanthaya
    Intellectual 990 points

    Shreyas,

    Yikes - I just found this. Page 6-2 of the Bios v6 User's Guide (SPRUEX3G) warns of dire consequences if CSL and SYS BIOS are used together for interrupt, timer or cache functions. While different than CSL,  I think I grasp the xdc calling sequence where the affected of cache (L1P, L1D, ALLD,  etc) is included in the call. However, this brings up another question relating to the Shared Memory Controller (SMC) for C6486/C6472 DSPs. The online help for the ...CACHE modules do not mention configuring the SL2RAM prefetch controller (cache like).  Currently we use CSL (csl_smc.h) to configure it. Wha tis the XDC safe way to do this?

    Current code:

     

     

    unsigned int  prefetch_blocks;
    CSL_SmcHandle hSmc;
    CSL_SmcObj smcObj;
    CSL_Status status;

    ...

    // Enable all except 64k block from 0x00200000 to 0x00210000

     

     

    prefetch_blocks = 0xFFFE0000;
    hSmc     = CSL_smcOpen(&smcObj, CSL_SMC_0, NULL, &status);
    CSL_smcHwControl(hSmc, CSL_SMC_CMD_ENA_PREFETCH_PAGE, &prefetch_blocks);

    Thanks,

    Calvin

  • 0 in reply to CalvinC
    Genius 4375 points

    I should have clarified this in my earlier post and I apologize for the confusion.  If you are using SYS/BIOS, you cannot use CSL cache APIs that perform cache-related initialization since they would stomp over initialization performed by SYS/BIOS under-the-hood.

    However, CSL CACHE writeback/invalidate APIs should still work alongside their BIOS 6 counterparts provided the right type of context protection is used with the APIs.  That said, the BIOS 6 users guide correctly recommends against using the CSL CACHE APIs with SYS/BIOS since the SYS/BIOS versions are better designed to work alongside the various types of SYS/BIOS threads.

    Most SYS/BIOS cache configuration is performed via your .cfg file or via your RTSC platform.  However, there are also some runtime APIs that can be used to configure the cache at runtime.   You can find more information about the configuring SYS/BIOS cache module by reading the cdoc for the ti.sysbios.family.c64p.Cache module.

    Regarding your last question regarding the SL2RAM prefetch controller: I'm not very familiar with this component so I'll enlist help from some more knowledgeable sources to answer your question.

    Regards,

    Shreyas

  • 0 in reply to Shreyas Oppanthaya
    Intellectual 990 points

    Shreyas,

     

    Thanks for the update. We can accomdate the cache restrictions but heavily rely on CSL for other HW interfaces like SRIO. Any conflict there is a BIG issue. One would hope the BIOS guys and the CSL guys talk to each other since users need both not one OR the other.

     

    Thanks,

    Calvin