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C64x - TMS320C6410ZTS400

Former Member
Former Member
Other Parts Discussed in Thread: TMS320C6410

Date Opened:          3/24/2011 12:10:09 PM
Company Name:      Avnet
Contact Name:        Mehdi Tamehi
Contact Phone:        (604) 444-3836
Contact Email:         mehdi.tamehi@avnet.com
Address:                  8608 Commerce Court
City and State:         Burnaby, BC
Postal Code:            V5A4N6

SILICON Support, C64x, Other DSP Silicon related issue

My customer is using the TMS320C6410. It is connected to 2 Micron SDRAM MT48LC16M16A2 to have a 32 bit data bus. The \CE0 (DSP) is connected to the two \CS of SDRAMs. This set up works just fine. They want to expand more RAM. They then connect another pair of Micron SDRAM MT48LC16M16A2 to have a 32 bit data bus. The \CE1 (DSP) is connected to the two \CS of SDRAMs. It seems like they have some aliasing happening. Anytime they write to the second set of SDRAM, they actually overwrite the content of the first set of SDRAM�s!!! I have been reviewing datasheet. There is no registers to define the memory block to enable the CE0 and CE1. So how do we define the memory block for each CE0 and CE1? The marking on the DSP is: TMS 320C6410ZTS400 CA-87A0L2W Is this DSP affected with the TMS320C6410 errata? http://focus.ti.com/lit/er/sprz219c/sprz219c.pdf

  • 0
    TI__Guru* 84110 points

    For the addressing range of the EMIF, please refer to the TMS320C6410 data manual, SPRS247, and find the Memory Map Summary in Table 2-2. The second page of Table 2-2, on page 23 (document rev f), shows the address ranges for the four Chip Enable spaces.

    The SDRAMs on CE0 are accessed using addresses 0x80000000-0x81FFFFFF and the SDRAMs on CE1 are accessed using addresses 0x90000000-0x81FFFFFF.

    To what address are they writing when they get the aliasing, 0x82000000-0x82FFFFFF?

    Regards,
    RandyP

     

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