Other Parts Discussed in Thread: SN74CBTLV16292, CDCLVC1102
We are creating a design based on AM335X_ICE Eval Board (Made by TI), the big differences is Processor and interfaces. In this design PRU MII and MII interfaces are used, in my design PRU MII and RGMII interfaces are used.
Processor: AM5726
Mux: SN74CBTLV16292
PHY: DP83867IRPAPR
We want to create a board that can use either RGMII or PRU MII (It will use one or the other, no need for both at same time). Due to other features on the board we are limited to the following pins on the AM5726 processor:
Pins: U5, V5, W2, Y2, V3, V4, W9, V9, U6, V6, U7, V7 (PRU MII Only pins: V1, Y1, V2, U4)
These pins are able to be pinmux to either RGMII0 interface signals or PRU1 MII0 interface signals. The plan is to have 2 different pin mux files in our U-boot, and to choose the pin mux file dependent on whether the board will exhibit RGMII ethernet, or PRU MII ethernet.
We take each one of these pins above and put them through the A ports on the SN74CBTLV16292 mux, on the other side of the mux, all RGMII0 signals go through B1 ports, and all PRU MII signals go through B2 ports on the mux. We chose the TI analog mux in this case, since the signals can come from either side of the mux.
On the other side of the mux, the data and control signals are T-off in daisy chain fashion and then connected to the DP83867IRPAPR Phy. This way we would just need 1 PHY and we can configure PHY based on RGMII or PRU MII interface. Example (RXD0 comes out of the PHY at pin 44, it is then connected to pin 3B1 on the mux (pin 50), and then pin 50 on the mux is routed to pin 35 on the mux, 9B2, in order to minimize the stub that will exist from sharing the Data/Control signals between the RGMII and PRU interfaces.
The nice part is that this PHY generates a separate TX CLK (GTX TX CLK) for either RGMII or MII interface, therefore those signals are point-to-point (single-ended). The RXCLK is shared from the PHY for both RGMII and PRU MII interfaces, therefore we are using a clock buffer (CDCLVC1102) with minimal propagation delay to meet the spec of both processor and phy, and this allows the RXCLK to be point-to-point from PHY to Processor.
We wanted to run this design by TI Experts or others to see if you can find any issues that might come up with this concept, or if you believe this concept should work. I can upload a page of the schematic that shows the signals if my explanation wasn't clear enough.
