AM5728: Debug messages over UART

Hi Anton,

Can you connect to CCS and check if the intented padconfig registers have the right setting?

If not check the code again to see if you have changed the right config array in mux_data.h.

Regards,
Keerthy

Thanks you.

I get messages in my terminal from uart!

The problem was that my board has no eeprom and registers configuration not applied. I changed board.c and board_detect.c files and now i see messages in terminal (but u-boot not load properly).

I am interested SysConfig now. This tool can help me to get mux_data.h file and dts file for my custom board. Am i right?

Is there config file (file for SysConfig tool) that describes configuration of tiam5728evm?

I would like to load this file to SysConfig and change it for my custom board in order to not make config file from scratch.

Also when i turn on my board i have messages:

"<debug_uart> i2c_write: error waiting for addr ACK (status=0x116)
Scaling voltage failed for 0x2f
i2c_write: error waiting for addr ACK (status=0x116)
Scaling voltage failed for 0x23
i2c_write: error waiting for addr ACK (status=0x116)
Scaling voltage failed for 0x2b
No serial driver found
resetting ..."

I found that this messages print from omap24xx_i2c.c driver and clocks-common.c but i not understand from where functions called yet

Hi Anton,

scale_vcores function will be setting voltages of multiple voltage rails.

Anton Khrenkov said:

Scaling voltage failed for 0x2f
i2c_write: error waiting for addr ACK (status=0x116)
Scaling voltage failed for 0x23
i2c_write: error waiting for addr ACK (status=0x116)
Scaling voltage failed

All of them are related to that function. Hope your board specific PMIC is configured properly?

Is it same PMIC & same Slave ID?

- Keerthy

Hi, Keerthy J.

Sorry for delayed reply. I studied how porting u-boot and debug with jtag.

As I understand the main difference between evm and my custom board is no pmic. I removed some functions calls from code (scale_scores() for example) and set corresponding configs (configs/myboard_defconfig, include/configs/myboard.h).

I successfully load spl and u-boot from jtag (got jtag command prompt). But when I try load system from sd card I got message "Error, wrong i2c adapter 0 max 0 possible" from function i2c_get_adapter().

I changed configs that try to switch off pmic and i2c, but when i try to compile u-boot a have messages like "undefined reference to palmas_mmc1_poweron_ldo()". 

As i understand, u-boot code closely related with pmic and it cannot be absolutely independent from pmic. Or am I wrong? I attached my cfg files.

I think that I will have to change the code not only with #defines, but also change the content of the functions themselves.

Can you give me any advice? Am I choose i right way?

u-boot.cfg

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FIT_SOURCE ""
#define CONFIG_DEBUG_UART_ANNOUNCE 1
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_CMD_FAT 1
#define CONFIG_SPL_DM_SERIAL 1
#define CONFIG_BOOTM_NETBSD 1
#define CONFIG_OF_SPL_REMOVE_PROPS "pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_CMD_FDT 1
#define CONFIG_USB_GADGET_DOWNLOAD 1
#define CONFIG_CMD_ITEST 1
#define CONFIG_BOOTM_VXWORKS 1
#define CONFIG_CMD_EDITENV 1
#define CONFIG_FASTBOOT_GPT_NAME "gpt"
#define CONFIG_TI_SPI_MMAP 
#define CONFIG_CMD_PART 1
#define CONFIG_MISC 1
#define CONFIG_SPL_LOGLEVEL 5
#define CONFIG_SPL_USE_ARCH_MEMSET 1
#define CONFIG_HAS_VBAR 1
#define CONFIG_CMD_ENV_EXISTS 1
#define CONFIG_VERSION_VARIABLE 1
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SYS_LONGHELP 
#define CONFIG_SYS_MPUCLK 500
#define CONFIG_DEBUG_UART_BASE 0x48020000
#define CONFIG_IS_MODULE(option) config_enabled(CONFIG_VAL(option ##_MODULE))
#define CONFIG_FASTBOOT_BUF_SIZE 0x2F000000
#define CONFIG_ARM_CORTEX_A15_CVE_2017_5715 1
#define CONFIG_USE_ARCH_MEMSET 1
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_CMD_XIMG 1
#define CONFIG_EXPERT 1
#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 
#define CONFIG_CMDLINE 1
#define CONFIG_BOOTDELAY 2
#define CONFIG_CMD_BOOTEFI 1
#define CONFIG_ARCH_OMAP2PLUS 1
#define CONFIG_OF_EMBED 1
#define CONFIG_BOOTP_BOOTPATH 
#define CONFIG_SYS_HELP_CMD_WIDTH 8
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_EFI_PARTITION 1
#define CONFIG_SPL_SEPARATE_BSS 1
#define CONFIG_FS_FAT 1
#define CONFIG_SYS_ARM_CACHE_CP15 1
#define CONFIG_BOOTM_RTEMS 1
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_DM_I2C 1
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M
#define CONFIG_ARMV7_LPAE 1
#define CONFIG_MD5 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_BOOTM_LINUX 1
#define CONFIG_BOOTP_SEND_HOSTNAME 
#define CONFIG_DEFAULT_FDT_FILE ""
#define CONFIG_BOARD_LATE_INIT 1
#define CONFIG_CREATE_ARCH_SYMLINK 1
#define CONFIG_CMD_CONSOLE 1
#define CONFIG_SUPPORT_OF_CONTROL 1
#define CONFIG_SYS_CPU "armv7"
#define CONFIG_MII 
#define CONFIG_SPL_BOARD_INIT 1
#define CONFIG_SPL_STACK_R_ADDR 0x82000000
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x15
#define CONFIG_MMC_IO_VOLTAGE 1
#define CONFIG_BOOTP_GATEWAY 
#define CONFIG_SYS_THUMB_BUILD 1
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MMC 1
#define CONFIG_DM_ETH 1
#define CONFIG_SPL_OF_CONTROL 1
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
#define CONFIG_SPL_DISPLAY_PRINT 1
#define CONFIG_SPL_OS_BOOT 1
#define CONFIG_SMBIOS_PRODUCT_NAME "micran218"
#define CONFIG_CMD_MISC 1
#define CONFIG_FIT 1
#define CONFIG_MMC_UHS_SUPPORT 1
#define CONFIG_SPL_LIBCOMMON_SUPPORT 1
#define CONFIG_DEBUG_UART_CLOCK 48000000
#define CONFIG_PHY_GIGE 1
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_DM_DEVICE_REMOVE 1
#define CONFIG_MMC_WRITE 1
#define CONFIG_ENV_OVERWRITE 
#define CONFIG_CMD_NET 1
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_NFS 1
#define CONFIG_SPL_SYS_THUMB_BUILD 1
#define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
#define CONFIG_USB_XHCI_DWC3 1
#define CONFIG_SUPPORT_RAW_INITRD 
#define CONFIG_CMD_FS_GENERIC 1
#define CONFIG_CMD_PING 1
#define CONFIG_PHY_MICREL_KSZ90X1 1
#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_INITRD_TAG 
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_DRA7XX 1
#define CONFIG_SPL_LIBDISK_SUPPORT 1
#define CONFIG_USB_XHCI_DRA7XX_INDEX 0
#define CONFIG_LOCALVERSION ""
#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
#define CONFIG_IODELAY_RECALIBRATION 
#define CONFIG_DEBUG_UART 1
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_CC_OPTIMIZE_FOR_SIZE 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 1
#define CONFIG_SYS_DEF_EEPROM_ADDR 0
#define CONFIG_REGEX 1
#define CONFIG_EFI_PARTITION_ENTRIES_NUMBERS 128
#define CONFIG_SYS_CONFIG_NAME "am57xx_micran218"
#define CONFIG_SPL_SYS_MALLOC_SIMPLE 1
#define CONFIG_BOOTSTAGE_RECORD_COUNT 30
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_PIPE3_PHY 1
#define CONFIG_CMD_SAVEENV 1
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500
#define CONFIG_MKIMAGE_DTC_PATH "dtc"
#define CONFIG_SYS_ARM_MMU 1
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_BOOTM_PLAN9 1
#define CONFIG_IS_BUILTIN(option) config_enabled(CONFIG_VAL(option))
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_DM_MMC 1
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 31219
#define CONFIG_SERIAL_PRESENT 1
#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x100000
#define CONFIG_DM_MMC 1
#define CONFIG_SPL_EFI_PARTITION 1
#define CONFIG_FIT_ENABLE_SHA256_SUPPORT 1
#define CONFIG_OF_LIST "am57xx-beagle-micran218"
#define CONFIG_CMD_GPT 1
#define CONFIG_SCSI_AHCI 1
#define CONFIG_TPL_SYS_MALLOC_F_LEN 0x2000
#define CONFIG_ANDROID_BOOT_IMAGE 1
#define CONFIG_USE_BOOTARGS 1
#define CONFIG_USB_DWC3_PHY_OMAP 1
#define CONFIG_BOOTARGS "androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard"
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_DM_DEV_READ_INLINE 1
#define CONFIG_DM_WARN 1
#define CONFIG_BOOTP_DNS 
#define CONFIG_SYS_CACHE_SHIFT_6 1
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_ARM_ERRATA_798870 1
#define CONFIG_MMC_HW_PARTITIONING 1
#define CONFIG_SUPPORT_SPL 1
#define CONFIG_CMD_RUN 1
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_ENV_VARS_UBOOT_CONFIG 
#define CONFIG_DM_SPI_FLASH 1
#define CONFIG_TOOLS_DEBUG 1
#define CONFIG_USB 1
#define CONFIG_BOOTP_HOSTNAME 
#define CONFIG_BOARDDIR board/micran/micran218
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
#define CONFIG_OMAP_USB3PHY1_HOST 
#define CONFIG_SPL_LEGACY_IMAGE_SUPPORT 1
#define CONFIG_CPU_V7A 1
#define CONFIG_SPL_BOOTSTAGE_RECORD_COUNT 5
#define CONFIG_NET 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_USB_XHCI_OMAP 
#define CONFIG_USB_DWC3_GADGET 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_PHYLIB 1
#define CONFIG_GENERATE_SMBIOS_TABLE 1
#define CONFIG_CMDLINE_EDITING 
#define CONFIG_CMD_USB 1
#define CONFIG_DM_SERIAL 1
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_CMD_EXT2 1
#define CONFIG_CMD_EXT4 1
#define CONFIG_TI_EDMA3 
#define CONFIG_BOOTCOMMAND "if test ${dofastboot} -eq 1; then " "echo Boot fastboot requested, resetting dofastboot ...;" "setenv dofastboot 0; saveenv;" "echo Booting into fastboot ...; " "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " "fi;" "if test ${boot_fit} -eq 1; then " "run update_to_fit;" "fi;" "run findfdt; " "run envboot; " "run mmcboot;" "run emmc_linux_boot; " "run emmc_android_boot; " ""
#define CONFIG_QSPI_QUAD_SUPPORT 
#define CONFIG_ARCH_FIXUP_FDT_MEMORY 1
#define CONFIG_USB_GADGET_VENDOR_NUM 0x0451
#define CONFIG_SPL_SIMPLE_BUS 1
#define CONFIG_USB_XHCI_HCD 1
#define CONFIG_ISO_PARTITION 1
#define CONFIG_OMAP_USB2_PHY 1
#define CONFIG_SYS_MALLOC_CLEAR_ON_INIT 1
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_SYS_EXTRA_OPTIONS ""
#define CONFIG_EEPROM_BUS_ADDRESS 0
#define CONFIG_SPL_GPIO_SUPPORT 1
#define CONFIG_CMD_BOOTEFI_HELLO_COMPILE 1
#define CONFIG_HUSH_PARSER 1
#define CONFIG_CMD_DM 1
#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7"
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
#define CONFIG_DM 1
#define CONFIG_ZLIB 1
#define CONFIG_USB_GADGET_DUALSPEED 1
#define CONFIG_LIB_UUID 
#define CONFIG_BOOTP_DNS2 
#define CONFIG_OMAP54XX 1
#define CONFIG_CMD_GO 1
#define CONFIG_USB_HOST 1
#define CONFIG_CMD_BOOTD 1
#define CONFIG_CMD_BOOTM 1
#define CONFIG_SPL_SPI_FLASH_SUPPORT 1
#define CONFIG_CMD_BOOTZ 1
#define CONFIG_SYS_NS16550 1
#define CONFIG_SYS_MALLOC_F 1
#define CONFIG_AUTO_COMPLETE 
#define CONFIG_SYS_SOC "omap5"
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MALLOC_F_LEN 0x2000
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_USB_DWC3 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_GZIP 1
#define CONFIG_SYS_VENDOR "micran"
#define CONFIG_MMC_OMAP_HS 1
#define CONFIG_DM_I2C_COMPAT 
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200
#define CONFIG_DM_USB 1
#define CONFIG_TI_DRA7_THERMAL 1
#define CONFIG_REQUIRE_SERIAL_CONSOLE 1
#define CONFIG_TARGET_AM57XX_MICRAN218 1
#define CONFIG_IDENT_STRING ""
#define CONFIG_SYS_OMAP_ABE_SYSCK 
#define CONFIG_USB_DM_XHCI_OMAP 1
#define CONFIG_SCSI 1
#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
#define CONFIG_DRA7_IVA_OPP_HIGH 1
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_NS16550_COM1 UART1_BASE
#define CONFIG_SYS_NS16550_COM2 UART2_BASE
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_SPL_THERMAL 1
#define CONFIG_CMD_SPL_NAND_OFS 0x0
#define CONFIG_SPL_FIT 1
#define CONFIG_VAL(option) config_val(option)
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_DM_THERMAL 1
#define CONFIG_SPL_LIBGENERIC_SUPPORT 1
#define CONFIG_DM_STDIO 1
#define CONFIG_LOCALVERSION_AUTO 1
#define CONFIG_TI_QSPI 1
#define CONFIG_SUPPORT_EMMC_BOOT 
#define CONFIG_CMD_DDR3 1
#define CONFIG_SPL_MMC_SUPPORT 1
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#define CONFIG_FASTBOOT_USB_DEV 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_DRIVER_TI_CPSW 
#define CONFIG_IMAGE_FORMAT_LEGACY 
#define CONFIG_SYS_BOOT_RAMDISK_HIGH 
#define CONFIG_SPL_DMA_SUPPORT 1
#define CONFIG_DRA7_MPU_OPP_NOM 1
#define CONFIG_FASTBOOT_BUF_ADDR 0x82000000
#define CONFIG_NET_TFTP_VARS 1
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_USE_PRIVATE_LIBGCC 1
#define CONFIG_CMD_SPI 1
#define CONFIG_CMD_SPL 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_SPL_SERIAL_SUPPORT 1
#define CONFIG_HSMMC2_8BIT 
#define CONFIG_CMD_ECHO 1
#define CONFIG_SPL_SPI_LOAD 
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_REGMAP 1
#define CONFIG_USB_DWC3_OMAP 1
#define CONFIG_FAT_WRITE 1
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#define CONFIG_CMD_TIME 1
#define CONFIG_USE_ARCH_MEMCPY 1
#define CONFIG_SPL_FIT_GENERATOR ""
#define CONFIG_SPL_DM 1
#define CONFIG_SPL_ISO_PARTITION 1
#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
#define CONFIG_OF_CONTROL 1
#define CONFIG_EXTRA_ENV_SETTINGS DEFAULT_LINUX_BOOT_ENV DEFAULT_MMC_TI_ARGS DEFAULT_FIT_TI_ARGS DEFAULT_COMMON_BOOT_TI_ARGS DEFAULT_FDT_TI_ARGS DFUARGS NETARGS NANDARGS
#define CONFIG_EFI_PARTITION_ENTRIES_OFF 0
#define CONFIG_CMD_SCSI 1
#define CONFIG_BOOTP_PXE 
#define CONFIG_CMD_FASTBOOT 1
#define CONFIG_HAS_THUMB2 1
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_ARCH "arm"
#define CONFIG_CMD_ASKENV 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SPL_PARTITION_UUIDS 1
#define CONFIG_SYS_BOARD "micran218"
#define CONFIG_PARTITION_UUIDS 1
#define CONFIG_FASTBOOT 1
#define CONFIG_DM_GPIO 1
#define CONFIG_SYS_PTV 2
#define CONFIG_DTC 1
#define CONFIG_CMDLINE_TAG 
#define CONFIG_SYS_ARM_ARCH 7
#define CONFIG_SPL_USE_ARCH_MEMCPY 1
#define CONFIG_PALMAS_POWER 
#define CONFIG_BOOTSTAGE_STASH_SIZE 0x1000
#define CONFIG_OF_LIBFDT_OVERLAY 1
#define CONFIG_FASTBOOT_FLASH 1
#define CONFIG_CMD_IMPORTENV 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_MMC_QUIRKS 1
#define CONFIG_HAVE_PRIVATE_LIBGCC 1
#define CONFIG_CMD_EXPORTENV 1
#define CONFIG_PARTITIONS 1
#define CONFIG_SPL_DOS_PARTITION 1
#define CONFIG_OMAP_GPIO 1
#define CONFIG_OF_TRANSLATE 1
#define CONFIG_SPL_STACK_R 1
#define CONFIG_SCSI_AHCI_PLAT 
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_CMD_ELF 1
#define CONFIG_LIBATA 1
#define CONFIG_EFI_LOADER 1
#define CONFIG_DRA7_DSPEVE_OPP_HIGH 1
#define CONFIG_SMBIOS_MANUFACTURER "micran"
#define CONFIG_RANDOM_UUID 1
#define CONFIG_DM_SEQ_ALIAS 1
#define CONFIG_FS_EXT4 
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_FRAMEWORK 
#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
#define CONFIG_BOOTSTAGE_STASH_ADDR 0x0
#define CONFIG_SPI 
#define CONFIG_SPL 1
#define CONFIG_DRA7_GPU_OPP_HIGH 1
#define CONFIG_SPL_ENV_SUPPORT 1
#define CONFIG_CMD_SOURCE 1
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_USB_STORAGE 1
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_LOGLEVEL 5
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT 
#define CONFIG_SHA1 1
#define CONFIG_SETUP_MEMORY_TAGS 
#define CONFIG_CRC32 
#define CONFIG_EXT4_WRITE 
#define CONFIG_SPL_FAT_SUPPORT 1
#define CONFIG_SPL_SYS_MALLOC_F_LEN 0x2000
#define CONFIG_CMD_LOADB 1
#define CONFIG_CMD_LOADS 1
#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536
#define CONFIG_CMD_IMI 1
#define CONFIG_CMD_EXT4_WRITE 1
#define CONFIG_SF_DEFAULT_SPEED 76800000
#define CONFIG_SYSCON 1
#define CONFIG_CONS_INDEX 3
#define CONFIG_LMB 
#define CONFIG_AUTOBOOT 1
#define CONFIG_ARM 1
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
#define CONFIG_FASTBOOT_MBR_NAME "mbr"
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_PHY_MICREL 1
#define CONFIG_IS_ENABLED(option) (config_enabled(CONFIG_VAL(option)) || config_enabled(CONFIG_VAL(option ##_MODULE)))
#define CONFIG_CMD_GPIO 1
#define CONFIG_CMD_BDI 1
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1700
#define CONFIG_SHA256 1
#define CONFIG_BOOTP_SUBNETMASK 
#define CONFIG_DEBUG_UART_OMAP 1
#define CONFIG_NETDEVICES 1
#define CONFIG_DEFAULT_DEVICE_TREE "am57xx-beagle-micran218"
#define CONFIG_SPL_RAW_IMAGE_SUPPORT 1
#define CONFIG_USB_FUNCTION_FASTBOOT 1
#define CONFIG_USB_GADGET_MANUFACTURER "Texas Instruments"
#define CONFIG_CMD_MII 1
#define CONFIG_USB_GADGET 1
#define CONFIG_SPL_EXT_SUPPORT 1
#define CONFIG_I2C 
#define CONFIG_LIB_RAND 
#define CONFIG_SIMPLE_BUS 1
#define CONFIG_PHY 1
#define CONFIG_USB_GADGET_PRODUCT_NUM 0xd022
#define CONFIG_ARM_ASM_UNIFIED 1
#define CONFIG_FASTBOOT_FLASH_MMC 1
#define CONFIG_DEBUG_UART_SHIFT 2
#define CONFIG_CMD_MMC 1
#define CONFIG_SPL_SPI_SUPPORT 1
#define CONFIG_OMAP_USB_PHY 
#define CONFIG_DM_SPI 1
#define CONFIG_SPL_OF_LIBFDT 1
#define CONFIG_SPL_LOAD_FIT 1
#define CONFIG_SYS_I2C_BUS_MAX 5
#define CONFIG_SPL_SERIAL_PRESENT 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"

u-boot.cfg (spl)

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FIT_SOURCE ""
#define CONFIG_DEBUG_UART_ANNOUNCE 1
#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
#define CONFIG_CMD_FAT 1
#define CONFIG_SPL_DM_SERIAL 1
#define CONFIG_BOOTM_NETBSD 1
#define CONFIG_OF_SPL_REMOVE_PROPS "pinctrl-0 pinctrl-names clocks clock-names interrupt-parent"
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_CMD_FDT 1
#define CONFIG_USB_GADGET_DOWNLOAD 1
#define CONFIG_CMD_ITEST 1
#define CONFIG_BOOTM_VXWORKS 1
#define CONFIG_CMD_EDITENV 1
#define CONFIG_FASTBOOT_GPT_NAME "gpt"
#define CONFIG_TI_SPI_MMAP 
#define CONFIG_CMD_PART 1
#define CONFIG_MISC 1
#define CONFIG_SPL_LOGLEVEL 5
#define CONFIG_SPL_USE_ARCH_MEMSET 1
#define CONFIG_HAS_VBAR 1
#define CONFIG_CMD_ENV_EXISTS 1
#define CONFIG_VERSION_VARIABLE 1
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SYS_LONGHELP 
#define CONFIG_SYS_MPUCLK 500
#define CONFIG_DEBUG_UART_BASE 0x48020000
#define CONFIG_IS_MODULE(option) config_enabled(CONFIG_VAL(option ##_MODULE))
#define CONFIG_FASTBOOT_BUF_SIZE 0x2F000000
#define CONFIG_ARM_CORTEX_A15_CVE_2017_5715 1
#define CONFIG_USE_ARCH_MEMSET 1
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_CMD_XIMG 1
#define CONFIG_EXPERT 1
#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS 
#define CONFIG_CMDLINE 1
#define CONFIG_BOOTDELAY 2
#define CONFIG_CMD_BOOTEFI 1
#define CONFIG_ARCH_OMAP2PLUS 1
#define CONFIG_OF_EMBED 1
#define CONFIG_BOOTP_BOOTPATH 
#define CONFIG_SYS_HELP_CMD_WIDTH 8
#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_EFI_PARTITION 1
#define CONFIG_SPL_SEPARATE_BSS 1
#define CONFIG_FS_FAT 1
#define CONFIG_SYS_ARM_CACHE_CP15 1
#define CONFIG_BOOTM_RTEMS 1
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M
#define CONFIG_ARMV7_LPAE 1
#define CONFIG_MD5 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
#define CONFIG_BOOTM_LINUX 1
#define CONFIG_BOOTP_SEND_HOSTNAME 
#define CONFIG_DEFAULT_FDT_FILE ""
#define CONFIG_BOARD_LATE_INIT 1
#define CONFIG_CREATE_ARCH_SYMLINK 1
#define CONFIG_CMD_CONSOLE 1
#define CONFIG_SUPPORT_OF_CONTROL 1
#define CONFIG_SYS_CPU "armv7"
#define CONFIG_MII 
#define CONFIG_SPL_BOARD_INIT 1
#define CONFIG_SPL_STACK_R_ADDR 0x82000000
#define CONFIG_BOOTP_PXE_CLIENTARCH 0x15
#define CONFIG_MMC_IO_VOLTAGE 1
#define CONFIG_BOOTP_GATEWAY 
#define CONFIG_SYS_THUMB_BUILD 1
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_MMC 1
#define CONFIG_DM_ETH 1
#define CONFIG_SPL_OF_CONTROL 1
#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20))
#define CONFIG_SPL_DISPLAY_PRINT 1
#define CONFIG_SPL_OS_BOOT 1
#define CONFIG_SMBIOS_PRODUCT_NAME "micran218"
#define CONFIG_CMD_MISC 1
#define CONFIG_FIT 1
#define CONFIG_MMC_UHS_SUPPORT 1
#define CONFIG_SPL_LIBCOMMON_SUPPORT 1
#define CONFIG_DEBUG_UART_CLOCK 48000000
#define CONFIG_PHY_GIGE 1
#define CONFIG_ENV_OFFSET 0x260000
#define CONFIG_DM_DEVICE_REMOVE 1
#define CONFIG_MMC_WRITE 1
#define CONFIG_ENV_OVERWRITE 
#define CONFIG_CMD_NET 1
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_NFS 1
#define CONFIG_SPL_SYS_THUMB_BUILD 1
#define CONFIG_ENV_SIZE SZ_128K
#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
#define CONFIG_USB_XHCI_DWC3 1
#define CONFIG_SUPPORT_RAW_INITRD 
#define CONFIG_CMD_FS_GENERIC 1
#define CONFIG_CMD_PING 1
#define CONFIG_PHY_MICREL_KSZ90X1 1
#define CONFIG_SPL_BUILD 1
#define CONFIG_SYS_MALLOC_LEN SZ_32M
#define CONFIG_INITRD_TAG 
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_DRA7XX 1
#define CONFIG_SPL_LIBDISK_SUPPORT 1
#define CONFIG_USB_XHCI_DRA7XX_INDEX 0
#define CONFIG_LOCALVERSION ""
#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
#define CONFIG_IODELAY_RECALIBRATION 
#define CONFIG_DEBUG_UART 1
#define CONFIG_SYS_TEXT_BASE 0x80800000
#define CONFIG_CC_OPTIMIZE_FOR_SIZE 1
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR 1
#define CONFIG_SYS_DEF_EEPROM_ADDR 0
#define CONFIG_REGEX 1
#define CONFIG_EFI_PARTITION_ENTRIES_NUMBERS 128
#define CONFIG_SYS_CONFIG_NAME "am57xx_micran218"
#define CONFIG_SPL_SYS_MALLOC_SIMPLE 1
#define CONFIG_BOOTSTAGE_RECORD_COUNT 30
#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
#define CONFIG_PIPE3_PHY 1
#define CONFIG_CMD_SAVEENV 1
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500
#define CONFIG_MKIMAGE_DTC_PATH "dtc"
#define CONFIG_SYS_ARM_MMU 1
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_BOOTM_PLAN9 1
#define CONFIG_IS_BUILTIN(option) config_enabled(CONFIG_VAL(option))
#define CONFIG_SPL_TEXT_BASE 0x40300000
#define CONFIG_SPL_DM_MMC 1
#define CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC 31219
#define CONFIG_SERIAL_PRESENT 1
#define CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN 0x100000
#define CONFIG_DM_MMC 1
#define CONFIG_SPL_EFI_PARTITION 1
#define CONFIG_FIT_ENABLE_SHA256_SUPPORT 1
#define CONFIG_OF_LIST "am57xx-beagle-micran218"
#define CONFIG_CMD_GPT 1
#define CONFIG_SCSI_AHCI 1
#define CONFIG_TPL_SYS_MALLOC_F_LEN 0x2000
#define CONFIG_ANDROID_BOOT_IMAGE 1
#define CONFIG_USE_BOOTARGS 1
#define CONFIG_USB_DWC3_PHY_OMAP 1
#define CONFIG_BOOTARGS "androidboot.serialno=${serial#} console=ttyS2,115200 androidboot.console=ttyS2 androidboot.hardware=am57xevmboard"
#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
#define CONFIG_DM_DEV_READ_INLINE 1
#define CONFIG_BOOTP_DNS 
#define CONFIG_SYS_CACHE_SHIFT_6 1
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_ARM_ERRATA_798870 1
#define CONFIG_MMC_HW_PARTITIONING 1
#define CONFIG_SUPPORT_SPL 1
#define CONFIG_CMD_RUN 1
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_ENV_VARS_UBOOT_CONFIG 
#define CONFIG_DM_SPI_FLASH 1
#define CONFIG_TOOLS_DEBUG 1
#define CONFIG_USB 1
#define CONFIG_BOOTP_HOSTNAME 
#define CONFIG_BOARDDIR board/micran/micran218
#define CONFIG_CMD_SPL_WRITE_SIZE 0x2000
#define CONFIG_OMAP_USB3PHY1_HOST 
#define CONFIG_SPL_LEGACY_IMAGE_SUPPORT 1
#define CONFIG_CPU_V7A 1
#define CONFIG_SPL_BOOTSTAGE_RECORD_COUNT 5
#define CONFIG_NET 1
#define CONFIG_OF_LIBFDT 1
#define CONFIG_USB_XHCI_OMAP 
#define CONFIG_USB_DWC3_GADGET 1
#define CONFIG_SYS_MAX_FLASH_SECT 512
#define CONFIG_PHYLIB 1
#define CONFIG_GENERATE_SMBIOS_TABLE 1
#define CONFIG_CMDLINE_EDITING 
#define CONFIG_CMD_USB 1
#define CONFIG_DM_SERIAL 1
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_CMD_EXT2 1
#define CONFIG_CMD_EXT4 1
#define CONFIG_TI_EDMA3 
#define CONFIG_BOOTCOMMAND "if test ${dofastboot} -eq 1; then " "echo Boot fastboot requested, resetting dofastboot ...;" "setenv dofastboot 0; saveenv;" "echo Booting into fastboot ...; " "fastboot " __stringify(CONFIG_FASTBOOT_USB_DEV) "; " "fi;" "if test ${boot_fit} -eq 1; then " "run update_to_fit;" "fi;" "run findfdt; " "run envboot; " "run mmcboot;" "run emmc_linux_boot; " "run emmc_android_boot; " ""
#define CONFIG_QSPI_QUAD_SUPPORT 
#define CONFIG_ARCH_FIXUP_FDT_MEMORY 1
#define CONFIG_USB_GADGET_VENDOR_NUM 0x0451
#define CONFIG_SPL_SIMPLE_BUS 1
#define CONFIG_USB_XHCI_HCD 1
#define CONFIG_ISO_PARTITION 1
#define CONFIG_OMAP_USB2_PHY 1
#define CONFIG_SYS_MALLOC_CLEAR_ON_INIT 1
#define CONFIG_NET_RETRY_COUNT 10
#define CONFIG_SYS_EXTRA_OPTIONS ""
#define CONFIG_EEPROM_BUS_ADDRESS 0
#define CONFIG_SPL_GPIO_SUPPORT 1
#define CONFIG_CMD_BOOTEFI_HELLO_COMPILE 1
#define CONFIG_HUSH_PARSER 1
#define CONFIG_CMD_DM 1
#define CONFIG_BOOTP_VCI_STRING "U-Boot.armv7"
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
#define CONFIG_DM 1
#define CONFIG_ZLIB 1
#define CONFIG_USB_GADGET_DUALSPEED 1
#define CONFIG_LIB_UUID 
#define CONFIG_BOOTP_DNS2 
#define CONFIG_OMAP54XX 1
#define CONFIG_CMD_GO 1
#define CONFIG_USB_HOST 1
#define CONFIG_CMD_BOOTD 1
#define CONFIG_CMD_BOOTM 1
#define CONFIG_SPL_SPI_FLASH_SUPPORT 1
#define CONFIG_CMD_BOOTZ 1
#define CONFIG_SYS_NS16550 1
#define CONFIG_SYS_MALLOC_F 1
#define CONFIG_AUTO_COMPLETE 
#define CONFIG_SYS_SOC "omap5"
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_ENV_IS_IN_MMC 1
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MALLOC_F_LEN 0x2000
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_USB_DWC3 1
#define CONFIG_DOS_PARTITION 1
#define CONFIG_GZIP 1
#define CONFIG_SYS_VENDOR "micran"
#define CONFIG_MMC_OMAP_HS 1
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200
#define CONFIG_DM_USB 1
#define CONFIG_TI_DRA7_THERMAL 1
#define CONFIG_REQUIRE_SERIAL_CONSOLE 1
#define CONFIG_TARGET_AM57XX_MICRAN218 1
#define CONFIG_IDENT_STRING ""
#define CONFIG_SYS_OMAP_ABE_SYSCK 
#define CONFIG_USB_DM_XHCI_OMAP 1
#define CONFIG_SCSI 1
#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000
#define CONFIG_DRA7_IVA_OPP_HIGH 1
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_NS16550_COM1 UART1_BASE
#define CONFIG_SYS_NS16550_COM2 UART2_BASE
#define CONFIG_SYS_NS16550_COM3 UART3_BASE
#define CONFIG_SPL_THERMAL 1
#define CONFIG_CMD_SPL_NAND_OFS 0x0
#define CONFIG_SPL_FIT 1
#define CONFIG_VAL(option) config_val(option)
#define CONFIG_SYS_LOAD_ADDR 0x82000000
#define CONFIG_DM_THERMAL 1
#define CONFIG_SPL_LIBGENERIC_SUPPORT 1
#define CONFIG_LOCALVERSION_AUTO 1
#define CONFIG_TI_QSPI 1
#define CONFIG_SUPPORT_EMMC_BOOT 
#define CONFIG_CMD_DDR3 1
#define CONFIG_SPL_MMC_SUPPORT 1
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#define CONFIG_FASTBOOT_USB_DEV 1
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_DRIVER_TI_CPSW 
#define CONFIG_IMAGE_FORMAT_LEGACY 
#define CONFIG_SYS_BOOT_RAMDISK_HIGH 
#define CONFIG_SPL_DMA_SUPPORT 1
#define CONFIG_DRA7_MPU_OPP_NOM 1
#define CONFIG_FASTBOOT_BUF_ADDR 0x82000000
#define CONFIG_NET_TFTP_VARS 1
#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
#define CONFIG_USE_PRIVATE_LIBGCC 1
#define CONFIG_CMD_SPI 1
#define CONFIG_CMD_SPL 1
#define CONFIG_CMD_DHCP 1
#define CONFIG_SPL_SERIAL_SUPPORT 1
#define CONFIG_HSMMC2_8BIT 
#define CONFIG_CMD_ECHO 1
#define CONFIG_SPL_SPI_LOAD 
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_REGMAP 1
#define CONFIG_USB_DWC3_OMAP 1
#define CONFIG_FAT_WRITE 1
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#define CONFIG_CMD_TIME 1
#define CONFIG_USE_ARCH_MEMCPY 1
#define CONFIG_SYS_I2C 
#define CONFIG_SPL_FIT_GENERATOR ""
#define CONFIG_SPL_DM 1
#define CONFIG_SPL_ISO_PARTITION 1
#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
#define CONFIG_OF_CONTROL 1
#define CONFIG_EXTRA_ENV_SETTINGS DEFAULT_LINUX_BOOT_ENV DEFAULT_MMC_TI_ARGS DEFAULT_FIT_TI_ARGS DEFAULT_COMMON_BOOT_TI_ARGS DEFAULT_FDT_TI_ARGS DFUARGS NETARGS NANDARGS
#define CONFIG_EFI_PARTITION_ENTRIES_OFF 0
#define CONFIG_CMD_SCSI 1
#define CONFIG_BOOTP_PXE 
#define CONFIG_CMD_FASTBOOT 1
#define CONFIG_HAS_THUMB2 1
#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_ARCH "arm"
#define CONFIG_CMD_ASKENV 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SPL_PARTITION_UUIDS 1
#define CONFIG_SYS_BOARD "micran218"
#define CONFIG_PARTITION_UUIDS 1
#define CONFIG_FASTBOOT 1
#define CONFIG_DM_GPIO 1
#define CONFIG_SYS_PTV 2
#define CONFIG_DTC 1
#define CONFIG_CMDLINE_TAG 
#define CONFIG_SYS_ARM_ARCH 7
#define CONFIG_SPL_USE_ARCH_MEMCPY 1
#define CONFIG_PALMAS_POWER 
#define CONFIG_BOOTSTAGE_STASH_SIZE 0x1000
#define CONFIG_OF_LIBFDT_OVERLAY 1
#define CONFIG_FASTBOOT_FLASH 1
#define CONFIG_CMD_IMPORTENV 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_MMC_QUIRKS 1
#define CONFIG_HAVE_PRIVATE_LIBGCC 1
#define CONFIG_CMD_EXPORTENV 1
#define CONFIG_PARTITIONS 1
#define CONFIG_SPL_DOS_PARTITION 1
#define CONFIG_OMAP_GPIO 1
#define CONFIG_OF_TRANSLATE 1
#define CONFIG_SPL_STACK_R 1
#define CONFIG_SCSI_AHCI_PLAT 
#define CONFIG_SYS_MMC_ENV_PART 0
#define CONFIG_CMD_ELF 1
#define CONFIG_LIBATA 1
#define CONFIG_EFI_LOADER 1
#define CONFIG_DRA7_DSPEVE_OPP_HIGH 1
#define CONFIG_SMBIOS_MANUFACTURER "micran"
#define CONFIG_RANDOM_UUID 1
#define CONFIG_DM_SEQ_ALIAS 1
#define CONFIG_FS_EXT4 
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - CONFIG_SPL_TEXT_BASE)
#define CONFIG_SPL_FRAMEWORK 
#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000
#define CONFIG_BOOTSTAGE_STASH_ADDR 0x0
#define CONFIG_SPI 
#define CONFIG_SPL 1
#define CONFIG_DRA7_GPU_OPP_HIGH 1
#define CONFIG_SPL_ENV_SUPPORT 1
#define CONFIG_CMD_SOURCE 1
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_USB_STORAGE 1
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_LOGLEVEL 5
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT 
#define CONFIG_SHA1 1
#define CONFIG_SETUP_MEMORY_TAGS 
#define CONFIG_EXT4_WRITE 
#define CONFIG_SPL_FAT_SUPPORT 1
#define CONFIG_SPL_SYS_MALLOC_F_LEN 0x2000
#define CONFIG_CMD_LOADB 1
#define CONFIG_CMD_LOADS 1
#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536
#define CONFIG_CMD_IMI 1
#define CONFIG_CMD_EXT4_WRITE 1
#define CONFIG_SF_DEFAULT_SPEED 76800000
#define CONFIG_SYSCON 1
#define CONFIG_CONS_INDEX 3
#define CONFIG_LMB 
#define CONFIG_AUTOBOOT 1
#define CONFIG_ARM 1
#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000
#define CONFIG_FASTBOOT_MBR_NAME "mbr"
#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
#define CONFIG_PHY_MICREL 1
#define CONFIG_IS_ENABLED(option) (config_enabled(CONFIG_VAL(option)) || config_enabled(CONFIG_VAL(option ##_MODULE)))
#define CONFIG_CMD_GPIO 1
#define CONFIG_CMD_BDI 1
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 
#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1700
#define CONFIG_SHA256 1
#define CONFIG_BOOTP_SUBNETMASK 
#define CONFIG_DEBUG_UART_OMAP 1
#define CONFIG_NETDEVICES 1
#define CONFIG_DEFAULT_DEVICE_TREE "am57xx-beagle-micran218"
#define CONFIG_SPL_RAW_IMAGE_SUPPORT 1
#define CONFIG_USB_FUNCTION_FASTBOOT 1
#define CONFIG_USB_GADGET_MANUFACTURER "Texas Instruments"
#define CONFIG_CMD_MII 1
#define CONFIG_USB_GADGET 1
#define CONFIG_SPL_EXT_SUPPORT 1
#define CONFIG_I2C 
#define CONFIG_LIB_RAND 
#define CONFIG_SIMPLE_BUS 1
#define CONFIG_PHY 1
#define CONFIG_USB_GADGET_PRODUCT_NUM 0xd022
#define CONFIG_ARM_ASM_UNIFIED 1
#define CONFIG_FASTBOOT_FLASH_MMC 1
#define CONFIG_DEBUG_UART_SHIFT 2
#define CONFIG_CMD_MMC 1
#define CONFIG_SPL_SPI_SUPPORT 1
#define CONFIG_OMAP_USB_PHY 
#define CONFIG_DM_SPI 1
#define CONFIG_SPL_OF_LIBFDT 1
#define CONFIG_SPL_LOAD_FIT 1
#define CONFIG_SYS_I2C_BUS_MAX 5
#define CONFIG_SPL_SERIAL_PRESENT 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"

Hi,

palmas_mmc1_poweron_ldo

This is needed for MMC. You can try to comment that out as well. Yes there are some calls out of the palmas pmic driver as well.

Just try to return from that function as the first statement.

Best Regards,
Keerthy

Hi, Keerthy J. 

Thank you for help. I solved issue above, but now have other problem.

For my system I build modified am57xx-evm-reva3.dtb.

I have only one mmc (mmc1), that is why I set mmc2 status disabled in am57xx-beagle-x15-common.dtsi and also disabled sound0.

Also i disabled mcasp3 in dra72-evm-common.dtsi.

I try set up "broken-cd" and "non-removable" (I used sd-card) for mmc1 but it has no effect.

This sd-card successful mounted in my host machine.

Can you give me some advice for solve this issue?

My log:

U-Boot SPL 2018.01-00561-gd2fd323-dirty (Aug 05 2021 - 14:38:39)
DRA752-GP ES2.0
Trying to boot from MMC1
no pinctrl state for default mode
MMC Device 1 not found
*** Warning - No MMC card found, using default environment


U-Boot 2018.01-00561-gd2fd323-dirty (Aug 05 2021 - 14:38:39 +0700)

CPU  : DRA752-GP ES2.0
Model: TI AM5728 MICRAN218 b
Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN
DRAM:  2 GiB
MMC:   OMAP SD/MMC: 0
MMC Device 1 not found
*** Warning - No MMC card found, using default environment

In:    serial@48020000
Out:   serial@48020000
Err:   serial@48020000
SCSI:  SATA link 0 timeout.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
Found 0 device(s).
Net:   
Could not get PHY for ethernet@48484000: addr 1

Warning: ethernet@48484000 using MAC address from ROM
eth0: ethernet@48484000
Hit any key to stop autoboot1:  0
unable to read ssr
switch to partitions #0, OK
mmc0 is current device
unable to read ssr
SD/MMC found on device 0
** Unable to read file boot.scr **
1538 bytes read in 17 ms (87.9 KiB/s)
Loaded env from uEnv.txt
Importing environment from mmc0 ...
unable to read ssr
switch to partitions #0, OK
mmc0 is current device
unable to read ssr
SD/MMC found on device 0
4022784 bytes read in 705 ms (5.4 MiB/s)
147750 bytes read in 155 ms (930.7 KiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 8ffd8000, end 8ffff125 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.79-gbde58ab01e (khrenkov@khrenkov-sitar) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #1 SMP PREEMPT Wed Aug 4 17:34:36 +07 2021
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: TI AM5728 EVM
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000fe400000
[    0.000000] OMAP4: Map 0x00000000ffd00000 to fe600000 for dram barrier
[    0.000000] On node 0 totalpages: 474368
[    0.000000] free_area_init_node: node 0, pgdat c1053d80, node_mem_map eeda2000
[    0.000000]   DMA zone: 1728 pages used for memmap
[    0.000000]   DMA zone: 0 pages reserved
[    0.000000]   DMA zone: 147456 pages, LIFO batch:31
[    0.000000]   HighMem zone: 326912 pages, LIFO batch:31
[    0.000000] DRA752 ES2.0
[    0.000000] percpu: Embedded 15 pages/cpu @eed29000 s31372 r8192 d21876 u61440
[    0.000000] pcpu-alloc: s31372 r8192 d21876 u61440 alloc=15*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 472640
[    0.000000] Kernel command line: console=ttyO2,115200n8 root=PARTUUID=a464469c-02 rw rootfstype=ext4 rootwait
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1675572K/1897472K available (8192K kernel code, 347K rwdata, 2564K rodata, 2048K init, 282K bss, 33484K reserved, 188416K cma-reserved, 1283072K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0a00000   (10208 kB)
[    0.000000]       .init : 0xc0e00000 - 0xc1000000   (2048 kB)
[    0.000000]       .data : 0xc1000000 - 0xc1056e98   ( 348 kB)
[    0.000000]        .bss : 0xc1058000 - 0xc109ebe0   ( 283 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Tasks RCU enabled.
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000017] Switching to timer-based delay loop, resolution 162ns
[    0.000348] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000357] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000862] Console: colour dummy device 80x30
[    0.000879] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
[    0.000887] This ensures that you still see kernel messages. Please
[    0.000894] update your kernel commandline.
[    0.000915] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.000931] pid_max: default: 32768 minimum: 301
[    0.001044] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001058] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001590] CPU: Testing write buffer coherency: ok
[    0.001628] CPU0: Spectre v2: using ICIALLU workaround
[    0.001823] /cpus/cpu@0 missing clock-frequency property
[    0.001843] /cpus/cpu@1 missing clock-frequency property
[    0.001854] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.039849] Setting up static identity map for 0x80200000 - 0x80200060
[    0.059858] Hierarchical SRCU implementation.
[    0.080047] EFI services will not be available.
[    0.099920] smp: Bringing up secondary CPUs ...
[    0.170290] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.170296] CPU1: Spectre v2: using ICIALLU workaround
[    0.170396] smp: Brought up 1 node, 2 CPUs
[    0.170407] SMP: Total of 2 processors activated (24.59 BogoMIPS).
[    0.170415] CPU: All CPU(s) started in HYP mode.
[    0.170423] CPU: Virtualization extensions available.
[    0.170961] devtmpfs: initialized
[    0.191853] random: get_random_u32 called from bucket_table_alloc+0x108/0x230 with crng_init=0
[    0.192100] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.192291] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.192307] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.196079] pinctrl core: initialized pinctrl subsystem
[    0.196526] DMI not present or invalid.
[    0.196789] NET: Registered protocol family 16
[    0.197829] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.198763] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.411125] cpuidle: using governor ladder
[    0.411157] cpuidle: using governor menu
[    0.419666] gpio gpiochip0: (gpio): added GPIO chardev (254:0)
[    0.419734] gpiochip_setup_dev: registered GPIOs 0 to 31 on device: gpiochip0 (gpio)
[    0.419793] OMAP GPIO hardware version 0.1
[    0.420460] gpio gpiochip1: (gpio): added GPIO chardev (254:1)
[    0.420530] gpiochip_setup_dev: registered GPIOs 32 to 63 on device: gpiochip1 (gpio)
[    0.421201] gpio gpiochip2: (gpio): added GPIO chardev (254:2)
[    0.421272] gpiochip_setup_dev: registered GPIOs 64 to 95 on device: gpiochip2 (gpio)
[    0.421932] gpio gpiochip3: (gpio): added GPIO chardev (254:3)
[    0.421996] gpiochip_setup_dev: registered GPIOs 96 to 127 on device: gpiochip3 (gpio)
[    0.422660] gpio gpiochip4: (gpio): added GPIO chardev (254:4)
[    0.422724] gpiochip_setup_dev: registered GPIOs 128 to 159 on device: gpiochip4 (gpio)
[    0.423386] gpio gpiochip5: (gpio): added GPIO chardev (254:5)
[    0.423449] gpiochip_setup_dev: registered GPIOs 160 to 191 on device: gpiochip5 (gpio)
[    0.424108] gpio gpiochip6: (gpio): added GPIO chardev (254:6)
[    0.424180] gpiochip_setup_dev: registered GPIOs 192 to 223 on device: gpiochip6 (gpio)
[    0.424837] gpio gpiochip7: (gpio): added GPIO chardev (254:7)
[    0.424905] gpiochip_setup_dev: registered GPIOs 224 to 255 on device: gpiochip7 (gpio)
[    0.446981] No ATAGs?
[    0.447054] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.447068] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.447474] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.447484] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.448015] OMAP DMA hardware revision 0.0
[    0.457678] edma 43300000.edma: memcpy is disabled
[    0.460923] edma 43300000.edma: TI EDMA DMA engine driver
[    0.467548] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.467921] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-mmcwl[0]' - status (0)
[    0.468167] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-com_3v6[0]'
[    0.468584] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-main_12v0[0]'
[    0.468808] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-evm_5v0[0]'
[    0.468858] evm_5v0: supplied by main_12v0
[    0.469110] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-vdd_3v3[0]'
[    0.469276] com_3v6: supplied by evm_5v0
[    0.469417] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-aic_dvdd[0]'
[    0.469768] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-vtt[0]' - status (0)
[    0.472286] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.472479] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.472716] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.472949] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.473301] omap-iommu 41501000.mmu: 41501000.mmu registered
[    0.473510] omap-iommu 41502000.mmu: 41502000.mmu registered
[    0.473768] iommu: Adding device 58820000.ipu to group 1
[    0.473859] iommu: Adding device 55020000.ipu to group 2
[    0.474017] iommu: Adding device 40800000.dsp to group 0
[    0.474275] iommu: Adding device 41000000.dsp to group 3
[    0.476599] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    0.477106] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
[    0.477590] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
[    0.477767] media: Linux media interface: v0.10
[    0.477808] Linux video capture interface: v2.00
[    0.477885] pps_core: LinuxPPS API ver. 1 registered
[    0.477893] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.477912] PTP clock support registered
[    0.477939] EDAC MC: Ver: 3.0.0
[    0.478185] dmi: Firmware registration failed.
[    0.478570] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.478844] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.479162] Advanced Linux Sound Architecture Driver Initialized.
[    0.479861] clocksource: Switched to clocksource arch_sys_counter
[    0.487582] NET: Registered protocol family 2
[    0.488102] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.488165] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.488291] TCP: Hash tables configured (established 8192 bind 8192)
[    0.488360] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.488392] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.488514] NET: Registered protocol family 1
[    0.488799] RPC: Registered named UNIX socket transport module.
[    0.488809] RPC: Registered udp transport module.
[    0.488818] RPC: Registered tcp transport module.
[    0.488825] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.488836] PCI: CLS 0 bytes, default 64
[    0.489717] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    0.489934] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.490928] workingset: timestamp_bits=14 max_order=19 bucket_order=5
[    0.494983] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.495472] NFS: Registering the id_resolver key type
[    0.495496] Key type id_resolver registered
[    0.495504] Key type id_legacy registered
[    0.495541] ntfs: driver 2.1.32 [Flags: R/O].
[    0.496848] bounce: pool size: 64 pages
[    0.496894] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.496905] io scheduler noop registered
[    0.496914] io scheduler deadline registered
[    0.497007] io scheduler cfq registered (default)
[    0.497017] io scheduler mq-deadline registered
[    0.497026] io scheduler kyber registered
[    0.501475] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    0.504699] dra7-pcie 51000000.pcie: Linked as a consumer to phy-4a094000.pciephy.1
[    0.504857] dra7-pcie 51000000.pcie: GPIO lookup for consumer (null)
[    0.504868] dra7-pcie 51000000.pcie: using device tree for GPIO lookup
[    0.504904] of_get_named_gpiod_flags: parsed 'gpios' property of node '/ocp/axi@0/pcie@51000000[0]' - status (0)
[    0.505072] OF: PCI: host bridge /ocp/axi@0/pcie@51000000 ranges:
[    0.505108] OF: PCI:    IO 0x20003000..0x20012fff -> 0x00000000
[    0.505130] OF: PCI:   MEM 0x20013000..0x2fffffff -> 0x20013000
[    1.505400] dra7-pcie 51000000.pcie: phy link never came up
[    1.505530] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
[    1.505543] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.505555] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.505566] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[    1.505599] pci 0000:00:00.0: [104c:8888] type 01 class 0x060400
[    1.505633] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit]
[    1.505695] pci 0000:00:00.0: supports D1
[    1.505705] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    1.505888] PCI: bus0: Fast back to back transfers disabled
[    1.505976] PCI: bus1: Fast back to back transfers enabled
[    1.506013] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff 64bit]
[    1.506032] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    1.506340] pcieport 0000:00:00.0: Signaling PME with IRQ 166
[    1.506465] pcieport 0000:00:00.0: AER enabled with IRQ 166
[    1.507234] pwm-backlight backlight: GPIO lookup for consumer enable
[    1.507245] pwm-backlight backlight: using device tree for GPIO lookup
[    1.507258] of_get_named_gpiod_flags: can't parse 'enable-gpios' property of node '/backlight[0]'
[    1.507270] of_get_named_gpiod_flags: can't parse 'enable-gpio' property of node '/backlight[0]'
[    1.507279] pwm-backlight backlight: using lookup tables for GPIO lookup
[    1.507289] pwm-backlight backlight: lookup for GPIO enable failed
[    1.507312] pwm-backlight backlight: backlight supply power not found, using dummy regulator
[    1.552413] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    1.555067] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 45, base_baud = 3000000) is a 8250
[    2.862004] console [ttyS2] enabled
[    2.866314] 48422000.serial: ttyS7 at MMIO 0x48422000 (irq = 46, base_baud = 3000000) is a 8250
[    2.876927] omap_rng 48090000.rng: Random Number Generator ver. 20
[    2.885340] tpd12s015 encoder: failed to find video source
[    2.891515] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    2.900239] connector-hdmi connector: failed to find video source
[    2.906453] panel-dpi display: GPIO lookup for consumer enable
[    2.912333] panel-dpi display: using device tree for GPIO lookup
[    2.918390] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    2.927852] panel-dpi display: GPIO lookup for consumer reset
[    2.933640] panel-dpi display: using device tree for GPIO lookup
[    2.939674] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    2.948345] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    2.956922] panel-dpi display: using lookup tables for GPIO lookup
[    2.963145] panel-dpi display: lookup for GPIO reset failed
[    2.968758] panel-dpi display: display supply vcc not found, using dummy regulator
[    2.976481] panel-dpi display: failed to find video source
[    2.992163] brd: module loaded
[    3.000645] loop: module loaded
[    3.006656] mdio_bus fixed-0: GPIO lookup for consumer reset
[    3.012373] mdio_bus fixed-0: using lookup tables for GPIO lookup
[    3.018497] mdio_bus fixed-0: lookup for GPIO reset failed
[    3.024060] libphy: Fixed MDIO Bus: probed
[    3.030776] mdio_bus 48485000.mdio: GPIO lookup for consumer reset
[    3.036985] mdio_bus 48485000.mdio: using device tree for GPIO lookup
[    3.043490] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    3.054606] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    3.065628] mdio_bus 48485000.mdio: using lookup tables for GPIO lookup
[    3.072292] mdio_bus 48485000.mdio: lookup for GPIO reset failed
[    3.129918] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    3.137613] libphy: 48485000.mdio: probed
[    3.143229] davinci_mdio: probe of 48485000.mdio failed with error -5
[    3.150248] cpsw 48484000.ethernet: Detected MACID = b0:7e:11:03:13:7a
[    3.156858] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[    3.163261] cpsw 48484000.ethernet: ALE Table size 1024
[    3.168520] cpsw 48484000.ethernet: device node lookup for pps timer failed
[    3.175564] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[    3.183451] cpsw 48484000.ethernet: cpsw: Detected MACID = b0:7e:11:03:13:7b
[    3.191721] i2c /dev entries driver
[    3.196114] IR NEC protocol handler initialized
[    3.200690] IR RC5(x/sz) protocol handler initialized
[    3.205765] IR RC6 protocol handler initialized
[    3.210330] IR JVC protocol handler initialized
[    3.214880] IR Sony protocol handler initialized
[    3.219516] IR SANYO protocol handler initialized
[    3.224255] IR Sharp protocol handler initialized
[    3.228979] IR MCE Keyboard/mouse protocol handler initialized
[    3.234849] IR XMP protocol handler initialized
[    3.269951] tmp102 0-0048: error reading config register
[    3.275419] tmp102: probe of 0-0048 failed with error -121
[    3.283826] sdhci: Secure Digital Host Controller Interface driver
[    3.290061] sdhci: Copyright(c) Pierre Ossman
[    3.294964] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.301591] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led0[0]' - status (0)
[    3.310625] no flags found for gpios
[    3.314322] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led1[0]' - status (0)
[    3.323344] no flags found for gpios
[    3.327025] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led2[0]' - status (0)
[    3.336044] no flags found for gpios
[    3.339723] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led3[0]' - status (0)
[    3.348742] no flags found for gpios
[    3.352817] ledtrig-cpu: registered to indicate activity on CPUs
[    3.362719] NET: Registered protocol family 10
[    3.367999] Segment Routing with IPv6
[    3.371763] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.378134] NET: Registered protocol family 17
[    3.382795] Key type dns_resolver registered
[    3.387195] omap_voltage_late_init: Voltage driver support not added
[    3.393595] Power Management for TI OMAP4+ devices.
[    3.398737] Registering SWP/SWPB emulation handler
[    3.415925] dmm 4e000000.dmm: workaround for errata i878 in use
[    3.423509] dmm 4e000000.dmm: initialized all PAT entries
[    3.429979] tpd12s015 encoder: failed to find video source
[    3.435764] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    3.444495] connector-hdmi connector: failed to find video source
[    3.450943] panel-dpi display: GPIO lookup for consumer enable
[    3.456804] panel-dpi display: using device tree for GPIO lookup
[    3.462883] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    3.472344] panel-dpi display: GPIO lookup for consumer reset
[    3.478116] panel-dpi display: using device tree for GPIO lookup
[    3.484170] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    3.492836] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    3.501413] panel-dpi display: using lookup tables for GPIO lookup
[    3.507623] panel-dpi display: lookup for GPIO reset failed
[    3.513250] panel-dpi display: display supply vcc not found, using dummy regulator
[    3.520988] panel-dpi display: failed to find video source
[    3.537837] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER5[0]' - status (0)
[    3.547504] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER4[0]' - status (0)
[    3.557146] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER3[0]' - status (0)
[    3.566783] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER2[0]' - status (0)
[    3.576432] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER1[0]' - status (0)
[    3.586167] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    3.593670] tpd12s015 encoder: failed to find video source
[    3.599449] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    3.600169] hctosys: unable to open rtc device (rtc0)
[    3.601036] vmmcwl_fixed: disabling
[    3.601043] vdd_3v3: disabling
[    3.601048] aic_dvdd_fixed: disabling
[    3.601056] pbias_mmc_omap5: disabling
[    3.601068] ALSA device list:
[    3.601071]   No soundcards found.
[    3.633656] connector-hdmi connector: failed to find video source
[    3.640162] panel-dpi display: GPIO lookup for consumer enable
[    3.646023] panel-dpi display: using device tree for GPIO lookup
[    3.652105] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    3.661571] panel-dpi display: GPIO lookup for consumer reset
[    3.667344] panel-dpi display: using device tree for GPIO lookup
[    3.673398] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    3.682066] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    3.690643] panel-dpi display: using lookup tables for GPIO lookup
[    3.696853] panel-dpi display: lookup for GPIO reset failed
[    3.702485] panel-dpi display: display supply vcc not found, using dummy regulator
[    3.710207] panel-dpi display: failed to find video source
[    3.716650] Waiting for root device PARTUUID=a464469c-02...

am57xx-beagle-x15-common.dtsi:

/*
 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra74x.dtsi"
#include "am57xx-commercial-grade.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
#include "dra74-ipu-dsp-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";

	aliases {
		rtc0 = &mcp_rtc;
		rtc1 = &tps659038_rtc;
		rtc2 = &rtc;
		display0 = &hdmi0;

		//sound0 = &sound0;
		sound1 = &hdmi;
	};

	chosen {
		stdout-path = &uart3;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_memory_region: ipu2-memory@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_memory_region: dsp1-memory@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_memory_region: ipu1-memory@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};

		dsp2_memory_region: dsp2-memory@9f000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9f000000 0x0 0x800000>;
			reusable;
			status = "okay";
		};
	};

	main_12v0: fixedregulator-main_12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "main_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	evm_5v0: fixedregulator-evm_5v0 {
		/* Output of TPS54531D */
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&main_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_3v3: fixedregulator-vdd_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vdd_3v3";
		vin-supply = <&regen1>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd_fixed";
		vin-supply = <&vdd_3v3>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vtt_fixed: fixedregulator-vtt {
		/* TPS51200 */
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		vin-supply = <&smps3_reg>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
	};

	leds {
		compatible = "gpio-leds";

		led0 {
			label = "beagle-x15:usr0";
			gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};

		led1 {
			label = "beagle-x15:usr1";
			gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "cpu0";
			default-state = "off";
		};

		led2 {
			label = "beagle-x15:usr2";
			gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "mmc0";
			default-state = "off";
		};

		led3 {
			label = "beagle-x15:usr3";
			gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "disk-activity";
			default-state = "off";
		};
	};

	gpio_fan: gpio_fan {
		/* Based on 5v 500mA AFB02505HHB */
		compatible = "gpio-fan";
		gpios =  <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
		gpio-fan,speed-map = <0     0>,
				     <13000 1>;
		#cooling-cells = <2>;
	};

	hdmi0: connector {
		compatible = "hdmi-connector";
		label = "hdmi";

		type = "a";

		port {
			hdmi_connector_in: endpoint {
				remote-endpoint = <&tpd12s015_out>;
			};
		};
	};

	tpd12s015: encoder {
		compatible = "ti,tpd12s015";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				tpd12s015_in: endpoint {
					remote-endpoint = <&hdmi_out>;
				};
			};

			port@1 {
				reg = <1>;

				tpd12s015_out: endpoint {
					remote-endpoint = <&hdmi_connector_in>;
				};
			};
		};
	};

	sound0: sound0 {
		status="disabled";
		compatible = "simple-audio-card";
		simple-audio-card,name = "BeagleBoard-X15";
		simple-audio-card,widgets =
			"Line", "Line Out",
			"Line", "Line In";
		simple-audio-card,routing =
			"Line Out",	"LLOUT",
			"Line Out",	"RLOUT",
			"MIC2L",	"Line In",
			"MIC2R",	"Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <&sound0_master>;
		simple-audio-card,frame-master = <&sound0_master>;
		simple-audio-card,bitclock-inversion;

		simple-audio-card,cpu {
			sound-dai = <&mcasp3>;
			status="disabled";
		};

		sound0_master: simple-audio-card,codec {
			sound-dai = <&tlv320aic3104>;
			clocks = <&clkout2_clk>;
		};
	};
};

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;

	tps659038: tps659038@58 {
		status="disabled";
		compatible = "ti,tps659038";
		reg = <0x58>;
		interrupt-parent = <&gpio1>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

		#interrupt-cells = <2>;
		interrupt-controller;

		ti,system-power-controller;
		ti,palmas-override-powerhold;

		tps659038_pmic {
			compatible = "ti,tps659038-pmic";

			regulators {
				smps12_reg: smps12 {
					/* VDD_MPU */
					regulator-name = "smps12";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps3_reg: smps3 {
					/* VDD_DDR */
					regulator-name = "smps3";
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps45_reg: smps45 {
					/* VDD_DSPEVE, VDD_IVA, VDD_GPU */
					regulator-name = "smps45";
					regulator-min-microvolt = < 850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps6_reg: smps6 {
					/* VDD_CORE */
					regulator-name = "smps6";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1150000>;
					regulator-always-on;
					regulator-boot-on;
				};

				/* SMPS7 unused */

				smps8_reg: smps8 {
					/* VDD_1V8 */
					regulator-name = "smps8";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				/* SMPS9 unused */

				ldo1_reg: ldo1 {
					/* VDD_SD / VDDSHV8  */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
					regulator-always-on;
				};

				ldo2_reg: ldo2 {
					/* VDD_SHV5 */
					regulator-name = "ldo2";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo3_reg: ldo3 {
					/* VDDA_1V8_PHYA */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo4_reg: ldo4 {
					/* VDDA_1V8_PHYB */
					regulator-name = "ldo4";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo9_reg: ldo9 {
					/* VDD_RTC */
					regulator-name = "ldo9";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldoln_reg: ldoln {
					/* VDDA_1V8_PLL */
					regulator-name = "ldoln";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldousb_reg: ldousb {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldousb";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
				};

				regen1: regen1 {
					/* VDD_3V3_ON */
					regulator-name = "regen1";
					regulator-boot-on;
					regulator-always-on;
				};
			};
		};

		tps659038_rtc: tps659038_rtc {
			compatible = "ti,palmas-rtc";
			interrupt-parent = <&tps659038>;
			interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
			wakeup-source;
		};

		tps659038_pwr_button: tps659038_pwr_button {
			compatible = "ti,palmas-pwrbutton";
			interrupt-parent = <&tps659038>;
			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
			wakeup-source;
			ti,palmas-long-press-seconds = <12>;
		};

		tps659038_gpio: tps659038_gpio {
			compatible = "ti,palmas-gpio";
			gpio-controller;
			#gpio-cells = <2>;
		};

		extcon_usb2: tps659038_usb {
			compatible = "ti,palmas-usb-vid";
			ti,enable-vbus-detection;
			vbus-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
		};

	};

	tmp102: tmp102@48 {
		compatible = "ti,tmp102";
		reg = <0x48>;
		interrupt-parent = <&gpio7>;
		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
		#thermal-sensor-cells = <1>;
	};

	tlv320aic3104: tlv320aic3104@18 {
		#sound-dai-cells = <0>;
		compatible = "ti,tlv320aic3104";
		reg = <0x18>;
		assigned-clocks = <&clkoutmux2_clk_mux>;
		assigned-clock-parents = <&sys_clk2_dclk_div>;

		status = "okay";
		adc-settle-ms = <40>;

		AVDD-supply = <&vdd_3v3>;
		IOVDD-supply = <&vdd_3v3>;
		DRVDD-supply = <&vdd_3v3>;
		DVDD-supply = <&aic_dvdd>;
	};

	eeprom: eeprom@50 {
		compatible = "atmel,24c32";
		reg = <0x50>;
	};
};

&i2c3 {
	status = "okay";
	clock-frequency = <400000>;

	mcp_rtc: rtc@6f {
		compatible = "microchip,mcp7941x";
		reg = <0x6f>;
		interrupts-extended = <&crossbar_mpu GIC_SPI 2 IRQ_TYPE_EDGE_RISING>,
				      <&dra7_pmx_core 0x424>;
		interrupt-names = "irq", "wakeup";

		vcc-supply = <&vdd_3v3>;
		wakeup-source;
	};
};

&gpio7 {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&cpu0 {
	vdd-supply = <&smps12_reg>;
	voltage-tolerance = <1>;
};

&uart3 {
	status = "okay";
	interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
			      <&dra7_pmx_core 0x3f8>;
};

&davinci_mdio {
	phy0: ethernet-phy@1 {
		reg = <1>;
	};

	phy1: ethernet-phy@2 {
		reg = <2>;
	};
};

&mac {
	status = "okay";
	dual_emac;
};

&cpsw_emac0 {
	phy-handle = <&phy0>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	phy-handle = <&phy1>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <2>;
};

&mmc1 {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&mmc1_pins_default>;

	bus-width = <4>;
	cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
};

&mmc2 {
	status = "disabled";

	pinctrl-names = "default";
	pinctrl-0 = <&mmc2_pins_default>;

	vmmc-supply = <&vdd_3v3>;
	vqmmc-supply = <&vdd_3v3>;
	bus-width = <8>;
	non-removable;
	no-1-8-v;
};

&sata {
	status = "okay";
};

&usb2_phy1 {
	phy-supply = <&ldousb_reg>;
};

&usb2_phy2 {
	phy-supply = <&ldousb_reg>;
};

&usb1 {
	dr_mode = "host";
};

&omap_dwc3_2 {
	extcon = <&extcon_usb2>;
};

&usb2 {
	/*
	 * Stand alone usage is peripheral only.
	 * However, with some resistor modifications
	 * this port can be used via expansion connectors
	 * as "host" or "dual-role". If so, provide
	 * the necessary dr_mode override in the expansion
	 * board's DT.
	 */
	dr_mode = "peripheral";
};

&cpu_trips {
	cpu_alert1: cpu_alert1 {
		temperature = <50000>; /* millicelsius */
		hysteresis = <2000>; /* millicelsius */
		type = "active";
	};
};

&cpu_cooling_maps {
	map1 {
		trip = <&cpu_alert1>;
		cooling-device = <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
	};
};

&thermal_zones {
	board_thermal: board_thermal {
		polling-delay-passive = <1250>; /* milliseconds */
		polling-delay = <1500>; /* milliseconds */

				/* sensor       ID */
		thermal-sensors = <&tmp102     0>;

		board_trips: trips {
			board_alert0: board_alert {
				temperature = <40000>; /* millicelsius */
				hysteresis = <2000>; /* millicelsius */
				type = "active";
			};

			board_crit: board_crit {
				temperature = <105000>; /* millicelsius */
				hysteresis = <0>; /* millicelsius */
				type = "critical";
			};
		};

		board_cooling_maps: cooling-maps {
			map0 {
				trip = <&board_alert0>;
				cooling-device =
				  <&gpio_fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
			};
		};
       };
};

&gpu {
	status = "ok";
};

&dss {
	status = "ok";

	vdda_video-supply = <&ldoln_reg>;
};

&bb2d {
	status = "okay";
};

&hdmi {
	status = "ok";
	vdda-supply = <&ldo4_reg>;

	port {
		hdmi_out: endpoint {
			remote-endpoint = <&tpd12s015_in>;
		};
	};
};

&pcie1_rc {
	status = "ok";
	gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};

&pcie1_ep {
	gpios = <&gpio2 8 GPIO_ACTIVE_LOW>;
};

&mcasp3 {
	#sound-dai-cells = <0>;
	assigned-clocks = <&mcasp3_ahclkx_mux>;
	assigned-clock-parents = <&sys_clkin2>;
	status = "disabled";

	op-mode = <0>;	/* MCASP_IIS_MODE */
	tdm-slots = <2>;
	/* 4 serializers */
	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 2 0 0
	>;
	tx-num-evt = <32>;
	rx-num-evt = <32>;
};

&pruss_soc_bus1 {
	status = "okay";

	pruss1: pruss@0 {
		status = "okay";
	};
};

&pruss_soc_bus2 {
	status = "okay";

	pruss2: pruss@0 {
		status = "okay";
	};
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_memory_region>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_memory_region>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_memory_region>;
};

&dsp2 {
	status = "okay";
	memory-region = <&dsp2_memory_region>;
};

I decompile my dtb. Maybe it helps.

/dts-v1/;

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
	interrupt-parent = <0x1>;
	model = "TI AM5728 EVM";

	fixedregulator-mmcwl {
		phandle = <0x24a>;
		enable-active-high;
		gpio = <0x1a5 0x8 0x0>;
		regulator-max-microvolt = <0x1b7740>;
		regulator-min-microvolt = <0x1b7740>;
		regulator-name = "vmmcwl_fixed";
		compatible = "regulator-fixed";
	};

	fixedregulator-com_3v6 {
		phandle = <0x249>;
		regulator-boot-on;
		regulator-always-on;
		vin-supply = <0x23f>;
		regulator-max-microvolt = <0x36ee80>;
		regulator-min-microvolt = <0x36ee80>;
		regulator-name = "com_3v6";
		compatible = "regulator-fixed";
	};

	backlight {
		phandle = <0x246>;
		pwms = <0x213 0x0 0xc350 0x0>;
		default-brightness-level = <0x8>;
		brightness-levels = <0x0 0xf3 0xf5 0xf7 0xf9 0xfb 0xfc 0xfd 0xff>;
		compatible = "pwm-backlight";
	};

	display {
		phandle = <0x24b>;
		label = "lcd";
		enable-gpios = <0xaf 0x5 0x0>;
		backlight = <0x246>;
		compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";

		port {

			endpoint {
				phandle = <0x248>;
				remote-endpoint = <0x247>;
			};
		};

		panel-timing {
			vsync-len = <0xd>;
			vsync-active = <0x0>;
			vfront-porch = <0x16>;
			vback-porch = <0xa>;
			vactive = <0x1e0>;
			pixelclk-active = <0x1>;
			hsync-len = <0x1e>;
			hsync-active = <0x0>;
			hfront-porch = <0xd2>;
			hback-porch = <0x10>;
			hactive = <0x320>;
			de-active = <0x1>;
			clock-frequency = <0x1f78a40>;
		};
	};

	gpio_keys {
		autorepeat;
		#size-cells = <0x0>;
		#address-cells = <0x1>;
		compatible = "gpio-keys";

		USER5 {
			linux,code = <0x66>;
			label = "Home";
			gpios = <0xaf 0x14 0x1>;
		};

		USER4 {
			linux,code = <0x6a>;
			label = "Right";
			gpios = <0xaf 0x18 0x1>;
		};

		USER3 {
			linux,code = <0x69>;
			label = "Left";
			gpios = <0xaf 0x1c 0x1>;
		};

		USER2 {
			linux,code = <0x6c>;
			label = "Down";
			gpios = <0xaf 0x19 0x1>;
		};

		USER1 {
			linux,code = <0x67>;
			label = "Up";
			gpios = <0xaf 0x17 0x1>;
		};
	};

	chosen {
		stdout-path = "/ocp/serial@48020000";
	};

	aliases {
		display1 = "/connector";
		i2c0 = "/ocp/i2c@48070000";
		i2c1 = "/ocp/i2c@48072000";
		i2c2 = "/ocp/i2c@48060000";
		i2c3 = "/ocp/i2c@4807a000";
		i2c4 = "/ocp/i2c@4807c000";
		serial0 = "/ocp/serial@4806a000";
		serial1 = "/ocp/serial@4806c000";
		serial2 = "/ocp/serial@48020000";
		serial3 = "/ocp/serial@4806e000";
		serial4 = "/ocp/serial@48066000";
		serial5 = "/ocp/serial@48068000";
		serial6 = "/ocp/serial@48420000";
		serial7 = "/ocp/serial@48422000";
		serial8 = "/ocp/serial@48424000";
		serial9 = "/ocp/serial@4ae2b000";
		ethernet0 = "/ocp/ethernet@48484000/slave@48480200";
		ethernet1 = "/ocp/ethernet@48484000/slave@48480300";
		d_can0 = "/ocp/can@4ae3c000";
		d_can1 = "/ocp/can@48480000";
		spi0 = "/ocp/qspi@4b300000";
		rproc0 = "/ocp/ipu@58820000";
		rproc1 = "/ocp/ipu@55020000";
		rproc2 = "/ocp/dsp@40800000";
		rproc3 = "/ocp/dsp@41000000";
		rtc0 = "/ocp/i2c@48060000/rtc@6f";
		rtc1 = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
		rtc2 = "/ocp/rtc@48838000";
		display0 = "/display";
		sound1 = "/ocp/dss@58000000/encoder@58060000";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <0x1 0xd 0x308 0x1 0xe 0x308 0x1 0xb 0x308 0x1 0xa 0x308>;
		interrupt-parent = <0x2>;
	};

	interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x0 0x48211000 0x0 0x1000 0x0 0x48212000 0x0 0x2000 0x0 0x48214000 0x0 0x2000 0x0 0x48216000 0x0 0x2000>;
		interrupts = <0x1 0x9 0x304>;
		interrupt-parent = <0x2>;
		phandle = <0x2>;
	};

	interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x0 0x48281000 0x0 0x1000>;
		interrupt-parent = <0x2>;
		phandle = <0x8>;
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
			operating-points-v2 = <0x3>;
			clocks = <0x4>;
			clock-names = "cpu";
			clock-latency = <0x493e0>;
			cooling-min-level = <0x0>;
			cooling-max-level = <0x2>;
			#cooling-cells = <0x2>;
			vbb-supply = <0x5>;
			vdd-supply = <0x6>;
			voltage-tolerance = <0x1>;
			phandle = <0x123>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
			operating-points-v2 = <0x3>;
		};
	};

	opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <0x7>;
		opp-shared;
		phandle = <0x3>;

		opp_nom-1000000000 {
			opp-hz = <0x0 0x3b9aca00>;
			opp-microvolt = <0x102ca0 0xcf850 0x118c30 0x102ca0 0xcf850 0x118c30>;
			opp-supported-hw = <0xff 0x1>;
			opp-suspend;
		};

		opp_od-1176000000 {
			opp-hz = <0x0 0x46185600>;
			opp-microvolt = <0x11b340 0xd8108 0x11b340 0x11b340 0xd8108 0x11b340>;
			opp-supported-hw = <0xff 0x2>;
		};

		opp_high@1500000000 {
			opp-hz = <0x0 0x59682f00>;
			opp-microvolt = <0x127690 0xe7ef0 0x1312d0 0x127690 0xe7ef0 0x1312d0>;
			opp-supported-hw = <0xff 0x4>;
		};
	};

	soc {
		compatible = "ti,omap-infra";

		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	ocp {
		compatible = "ti,dra7-l3-noc", "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x0 0x0 0x0 0xc0000000>;
		ti,hwmods = "l3_main_1", "l3_main_2";
		reg = <0x0 0x44000000 0x0 0x1000000 0x0 0x45000000 0x0 0x1000>;
		interrupts-extended = <0x1 0x0 0x4 0x4 0x8 0x0 0xa 0x4>;

		l4@4a000000 {
			compatible = "ti,dra7-l4-cfg", "simple-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4a000000 0x22c000>;
			phandle = <0x135>;

			scm@2000 {
				compatible = "ti,dra7-scm-core", "simple-bus";
				reg = <0x2000 0x2000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x2000 0x2000>;
				phandle = <0x136>;

				scm_conf@0 {
					compatible = "syscon", "simple-bus";
					reg = <0x0 0x1400>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;
					ranges = <0x0 0x0 0x1400>;
					phandle = <0x9>;

					pbias_regulator@e00 {
						compatible = "ti,pbias-dra7", "ti,pbias-omap";
						reg = <0xe00 0x4>;
						syscon = <0x9>;
						phandle = <0x137>;

						pbias_mmc_omap5 {
							regulator-name = "pbias_mmc_omap5";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x325aa0>;
							phandle = <0xd1>;
						};
					};

					clocks {
						#address-cells = <0x1>;
						#size-cells = <0x0>;
						phandle = <0x138>;

						dss_deshdcp_clk@558 {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0xa>;
							ti,bit-shift = <0x0>;
							reg = <0x558>;
							phandle = <0x139>;
						};

						ehrpwm0_tbclk@558 {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0xb>;
							ti,bit-shift = <0x14>;
							reg = <0x558>;
							phandle = <0x117>;
						};

						ehrpwm1_tbclk@558 {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0xb>;
							ti,bit-shift = <0x15>;
							reg = <0x558>;
							phandle = <0x118>;
						};

						ehrpwm2_tbclk@558 {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0xb>;
							ti,bit-shift = <0x16>;
							reg = <0x558>;
							phandle = <0x119>;
						};

						sys_32k_ck {
							#clock-cells = <0x0>;
							compatible = "ti,mux-clock";
							clocks = <0xc 0xd 0xd 0xd>;
							ti,bit-shift = <0x8>;
							reg = <0x6c4>;
							phandle = <0x51>;
						};
					};
				};

				pinmux@1400 {
					compatible = "ti,dra7-padconf", "pinctrl-single";
					reg = <0x1400 0x468>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#pinctrl-cells = <0x1>;
					#interrupt-cells = <0x1>;
					interrupt-controller;
					pinctrl-single,register-width = <0x20>;
					pinctrl-single,function-mask = <0x3fffffff>;
					phandle = <0xb5>;

					mmc1_pins_default {
						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
						phandle = <0xd2>;
					};

					mmc1_pins_default_no_clk_pu {
						pinctrl-single,pins = <0x354 0x40000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
						phandle = <0x13a>;
					};

					mmc1_pins_sdr12 {
						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
						phandle = <0xd5>;
					};

					mmc1_pins_hs {
						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
						phandle = <0xd4>;
					};

					mmc1_pins_sdr25 {
						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
						phandle = <0xd6>;
					};

					mmc1_pins_sdr50 {
						pinctrl-single,pins = <0x354 0x601a0 0x358 0x601a0 0x35c 0x601a0 0x360 0x601a0 0x364 0x601a0 0x368 0x601a0>;
						phandle = <0xd7>;
					};

					mmc1_pins_ddr50 {
						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
						phandle = <0xd8>;
					};

					mmc1_pins_sdr104 {
						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
						phandle = <0xda>;
					};

					mmc2_pins_default {
						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
						phandle = <0xdd>;
					};

					mmc2_pins_hs {
						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
						phandle = <0xde>;
					};

					mmc2_pins_ddr_3_3v_rev11 {
						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
						phandle = <0x13b>;
					};

					mmc2_pins_ddr_1_8v_rev11 {
						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
						phandle = <0x13c>;
					};

					mmc2_pins_ddr_rev20 {
						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
						phandle = <0xdf>;
					};

					mmc2_pins_hs200 {
						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
						phandle = <0x13d>;
					};

					mmc4_pins_default {
						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
						phandle = <0x13e>;
					};

					mmc4_pins_hs {
						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
						phandle = <0x13f>;
					};

					mmc3_pins_default {
						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
						phandle = <0x140>;
					};

					mmc3_pins_hs {
						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
						phandle = <0x141>;
					};

					mmc3_pins_sdr12 {
						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
						phandle = <0x142>;
					};

					mmc3_pins_sdr25 {
						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
						phandle = <0x143>;
					};

					mmc3_pins_sdr50 {
						pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
						phandle = <0x144>;
					};

					mmc4_pins_sdr12 {
						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
						phandle = <0x145>;
					};

					mmc4_pins_sdr25 {
						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
						phandle = <0x146>;
					};
				};

				scm_conf@1c04 {
					compatible = "syscon";
					reg = <0x1c04 0x20>;
					#syscon-cells = <0x2>;
					phandle = <0xae>;
				};

				scm_conf@1c24 {
					compatible = "syscon";
					reg = <0x1c24 0x24>;
					phandle = <0xac>;
				};

				dma-router@b78 {
					compatible = "ti,dra7-dma-crossbar";
					reg = <0xb78 0xfc>;
					#dma-cells = <0x1>;
					dma-requests = <0xcd>;
					ti,dma-safe-map = <0x0>;
					dma-masters = <0xe>;
					phandle = <0xb4>;
				};

				dma-router@c78 {
					compatible = "ti,dra7-dma-crossbar";
					reg = <0xc78 0x7c>;
					#dma-cells = <0x2>;
					dma-requests = <0xcc>;
					ti,dma-safe-map = <0x0>;
					dma-masters = <0xf>;
					phandle = <0xf7>;
				};
			};

			cm_core_aon@5000 {
				compatible = "ti,dra7-cm-core-aon";
				reg = <0x5000 0x2000>;
				phandle = <0x147>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					phandle = <0x148>;

					atl_clkin0_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x10>;
						phandle = <0x44>;
					};

					atl_clkin1_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x10>;
						phandle = <0x43>;
					};

					atl_clkin2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x10>;
						phandle = <0x42>;
					};

					atl_clkin3_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x10>;
						phandle = <0x41>;
					};

					hdmi_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x30>;
					};

					mlb_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0xa8>;
					};

					mlbp_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0xa9>;
					};

					pciesref_acs_clk_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x5f5e100>;
						phandle = <0x5b>;
					};

					ref_clkin0_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x46>;
					};

					ref_clkin1_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x47>;
					};

					ref_clkin2_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x48>;
					};

					ref_clkin3_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x49>;
					};

					rmii_clk_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x72>;
					};

					sdvenc_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x149>;
					};

					secure_32k_clk_src_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x8000>;
						phandle = <0x92>;
					};

					sys_clk32_crystal_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x8000>;
						phandle = <0xc>;
					};

					sys_clk32_pseudo_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x11>;
						clock-mult = <0x1>;
						clock-div = <0x262>;
						phandle = <0xd>;
					};

					virt_12000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0xb71b00>;
						phandle = <0x82>;
					};

					virt_13000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0xc65d40>;
						phandle = <0x14a>;
					};

					virt_16800000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1005900>;
						phandle = <0x84>;
					};

					virt_19200000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x124f800>;
						phandle = <0x85>;
					};

					virt_20000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1312d00>;
						phandle = <0x83>;
					};

					virt_26000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x18cba80>;
						phandle = <0x86>;
					};

					virt_27000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x19bfcc0>;
						phandle = <0x87>;
					};

					virt_38400000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x249f000>;
						phandle = <0x88>;
					};

					sys_clkin2 {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1588800>;
						phandle = <0x45>;
					};

					usb_otg_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x8f>;
					};

					video1_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x3a>;
					};

					video1_m2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x2f>;
					};

					video2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x3b>;
					};

					video2_m2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x2e>;
					};

					dpll_abe_ck@1e0 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-m4xen-clock";
						clocks = <0x12 0x13>;
						reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
						assigned-clocks = <0x14>;
						assigned-clock-rates = <0x2faf080>;
						phandle = <0x14>;
					};

					dpll_abe_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x14>;
						phandle = <0x15>;
					};

					dpll_abe_m2x2_ck@1f0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x15>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x16>;
					};

					abe_clk@108 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x16>;
						ti,max-div = <0x4>;
						reg = <0x108>;
						ti,index-power-of-two;
						phandle = <0x8a>;
					};

					dpll_abe_m2_ck@1f0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x14>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x70>;
					};

					dpll_abe_m3x2_ck@1f4 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x15>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f4>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x17>;
					};

					dpll_core_byp_mux@12c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x12c>;
						phandle = <0x18>;
					};

					dpll_core_ck@120 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-core-clock";
						clocks = <0x11 0x18>;
						reg = <0x120 0x124 0x12c 0x128>;
						phandle = <0x19>;
					};

					dpll_core_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x19>;
						phandle = <0x1a>;
					};

					dpll_core_h12x2_ck@13c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x13c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x1b>;
					};

					mpu_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x1c>;
					};

					dpll_mpu_ck@160 {
						#clock-cells = <0x0>;
						compatible = "ti,omap5-mpu-dpll-clock";
						clocks = <0x11 0x1c>;
						reg = <0x160 0x164 0x16c 0x168>;
						phandle = <0x4>;
					};

					dpll_mpu_m2_ck@170 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x4>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x170>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x1d>;
					};

					mpu_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1d>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x96>;
					};

					dsp_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x1e>;
					};

					dpll_dsp_byp_mux@240 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x1e>;
						ti,bit-shift = <0x17>;
						reg = <0x240>;
						phandle = <0x1f>;
					};

					dpll_dsp_ck@234 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x1f>;
						reg = <0x234 0x238 0x240 0x23c>;
						assigned-clocks = <0x20>;
						assigned-clock-rates = <0x23c34600>;
						phandle = <0x20>;
					};

					dpll_dsp_m2_ck@244 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x20>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x244>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x21>;
						assigned-clock-rates = <0x23c34600>;
						phandle = <0x21>;
					};

					iva_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x22>;
					};

					dpll_iva_byp_mux@1ac {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x22>;
						ti,bit-shift = <0x17>;
						reg = <0x1ac>;
						phandle = <0x23>;
					};

					dpll_iva_ck@1a0 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x23>;
						reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
						assigned-clocks = <0x24>;
						assigned-clock-rates = <0x45707d40>;
						phandle = <0x24>;
					};

					dpll_iva_m2_ck@1b0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x24>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1b0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x25>;
						assigned-clock-rates = <0x17257f16>;
						phandle = <0x25>;
					};

					iva_dclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x25>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x98>;
					};

					dpll_gpu_byp_mux@2e4 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x2e4>;
						phandle = <0x26>;
					};

					dpll_gpu_ck@2d8 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x26>;
						reg = <0x2d8 0x2dc 0x2e4 0x2e0>;
						assigned-clocks = <0x27>;
						assigned-clock-rates = <0x4c1d7940>;
						phandle = <0x27>;
					};

					dpll_gpu_m2_ck@2e8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x27>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2e8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x28>;
						assigned-clock-rates = <0x195f286b>;
						phandle = <0x28>;
					};

					dpll_core_m2_ck@130 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x19>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x130>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x29>;
					};

					core_dpll_out_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x29>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9a>;
					};

					dpll_ddr_byp_mux@21c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x21c>;
						phandle = <0x2a>;
					};

					dpll_ddr_ck@210 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x2a>;
						reg = <0x210 0x214 0x21c 0x218>;
						phandle = <0x2b>;
					};

					dpll_ddr_m2_ck@220 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x2b>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x220>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x8c>;
					};

					dpll_gmac_byp_mux@2b4 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x2b4>;
						phandle = <0x2c>;
					};

					dpll_gmac_ck@2a8 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x2c>;
						reg = <0x2a8 0x2ac 0x2b4 0x2b0>;
						phandle = <0x2d>;
					};

					dpll_gmac_m2_ck@2b8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x2d>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2b8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x8d>;
					};

					video2_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2e>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9c>;
					};

					video1_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2f>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9d>;
					};

					hdmi_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x30>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9e>;
					};

					per_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x17>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x5f>;
					};

					usb_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x17>;
						clock-mult = <0x1>;
						clock-div = <0x3>;
						phandle = <0x63>;
					};

					eve_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x31>;
					};

					dpll_eve_byp_mux@290 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x31>;
						ti,bit-shift = <0x17>;
						reg = <0x290>;
						phandle = <0x32>;
					};

					dpll_eve_ck@284 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x32>;
						reg = <0x284 0x288 0x290 0x28c>;
						phandle = <0x33>;
					};

					dpll_eve_m2_ck@294 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x33>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x294>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x34>;
					};

					eve_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x34>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0xa7>;
					};

					dpll_core_h13x2_ck@140 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x140>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x14b>;
					};

					dpll_core_h14x2_ck@144 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x144>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x73>;
					};

					dpll_core_h22x2_ck@154 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x154>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x3c>;
					};

					dpll_core_h23x2_ck@158 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x158>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x81>;
					};

					dpll_core_h24x2_ck@15c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x15c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x10e>;
					};

					dpll_ddr_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x2b>;
						phandle = <0x35>;
					};

					dpll_ddr_h11x2_ck@228 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x35>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x228>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x14c>;
					};

					dpll_dsp_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x20>;
						phandle = <0x36>;
					};

					dpll_dsp_m3x2_ck@248 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x36>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x248>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x37>;
						assigned-clock-rates = <0x17d78400>;
						phandle = <0x37>;
					};

					dpll_gmac_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x2d>;
						phandle = <0x38>;
					};

					dpll_gmac_h11x2_ck@2c0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x38>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x39>;
					};

					dpll_gmac_h12x2_ck@2c4 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x38>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c4>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x14d>;
					};

					dpll_gmac_h13x2_ck@2c8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x38>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0xe2>;
					};

					dpll_gmac_m3x2_ck@2bc {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x38>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2bc>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x14e>;
					};

					gmii_m_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x39>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x14f>;
					};

					hdmi_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x30>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x4f>;
					};

					hdmi_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x30>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x55>;
					};

					l3_iclk_div@100 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						ti,max-div = <0x2>;
						ti,bit-shift = <0x4>;
						reg = <0x100>;
						clocks = <0x1b>;
						ti,index-power-of-two;
						phandle = <0xa>;
					};

					l4_root_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0xa>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0xb>;
					};

					video1_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x3a>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x4d>;
					};

					video1_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x3a>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x53>;
					};

					video2_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x3b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x4e>;
					};

					video2_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x3b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x54>;
					};

					ipu1_gfclk_mux@520 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x16 0x3c>;
						ti,bit-shift = <0x18>;
						reg = <0x520>;
						assigned-clocks = <0x3d>;
						assigned-clock-parents = <0x3c>;
						phandle = <0x3d>;
					};

					mcasp1_ahclkr_mux@550 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x1c>;
						reg = <0x550>;
						phandle = <0xfa>;
					};

					mcasp1_ahclkx_mux@550 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x550>;
						phandle = <0xf9>;
					};

					mcasp1_aux_gfclk_mux@550 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x550>;
						phandle = <0xf8>;
					};

					timer5_gfclk_mux@558 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
						ti,bit-shift = <0x18>;
						reg = <0x558>;
						phandle = <0x150>;
					};

					timer6_gfclk_mux@560 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
						ti,bit-shift = <0x18>;
						reg = <0x560>;
						phandle = <0x151>;
					};

					timer7_gfclk_mux@568 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
						ti,bit-shift = <0x18>;
						reg = <0x568>;
						phandle = <0x152>;
					};

					timer8_gfclk_mux@570 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
						ti,bit-shift = <0x18>;
						reg = <0x570>;
						phandle = <0x153>;
					};

					uart6_gfclk_mux@580 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x580>;
						phandle = <0x154>;
					};

					dummy_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x155>;
					};
				};

				clockdomains {
					phandle = <0x156>;
				};
			};

			cm_core@8000 {
				compatible = "ti,dra7-cm-core";
				reg = <0x8000 0x3000>;
				phandle = <0x157>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					phandle = <0x158>;

					dpll_pcie_ref_ck@200 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x11>;
						reg = <0x200 0x204 0x20c 0x208>;
						phandle = <0x59>;
					};

					dpll_pcie_ref_m2ldo_ck@210 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x59>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x210>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x5a>;
					};

					apll_pcie_in_clk_mux@4ae06118 {
						compatible = "ti,mux-clock";
						clocks = <0x5a 0x5b>;
						#clock-cells = <0x0>;
						reg = <0x21c 0x4>;
						ti,bit-shift = <0x7>;
						phandle = <0x5c>;
					};

					apll_pcie_ck@21c {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-apll-clock";
						clocks = <0x5c 0x59>;
						reg = <0x21c 0x220>;
						phandle = <0x5d>;
					};

					optfclk_pciephy1_32khz@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0x8>;
						phandle = <0xe6>;
					};

					optfclk_pciephy2_32khz@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0x8>;
						phandle = <0xe9>;
					};

					optfclk_pciephy_div@4a00821c {
						compatible = "ti,divider-clock";
						clocks = <0x5d>;
						#clock-cells = <0x0>;
						reg = <0x21c>;
						ti,dividers = <0x2 0x1>;
						ti,bit-shift = <0x8>;
						ti,max-div = <0x2>;
						phandle = <0x5e>;
					};

					optfclk_pciephy1_clk@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x5d>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0x9>;
						phandle = <0xe7>;
					};

					optfclk_pciephy2_clk@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x5d>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0x9>;
						phandle = <0xea>;
					};

					optfclk_pciephy1_div_clk@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x5e>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0xa>;
						phandle = <0xe8>;
					};

					optfclk_pciephy2_div_clk@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x5e>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0xa>;
						phandle = <0xeb>;
					};

					apll_pcie_clkvcoldo {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5d>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x159>;
					};

					apll_pcie_clkvcoldo_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5d>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x15a>;
					};

					apll_pcie_m2_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5d>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x91>;
					};

					dpll_per_byp_mux@14c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x5f>;
						ti,bit-shift = <0x17>;
						reg = <0x14c>;
						phandle = <0x60>;
					};

					dpll_per_ck@140 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x60>;
						reg = <0x140 0x144 0x14c 0x148>;
						phandle = <0x61>;
					};

					dpll_per_m2_ck@150 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x61>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x150>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x62>;
					};

					func_96m_aon_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x62>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9f>;
					};

					dpll_usb_byp_mux@18c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x63>;
						ti,bit-shift = <0x17>;
						reg = <0x18c>;
						phandle = <0x64>;
					};

					dpll_usb_ck@180 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-j-type-clock";
						clocks = <0x11 0x64>;
						reg = <0x180 0x184 0x18c 0x188>;
						phandle = <0x65>;
					};

					dpll_usb_m2_ck@190 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x65>;
						ti,max-div = <0x7f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x190>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x68>;
					};

					dpll_pcie_ref_m2_ck@210 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x59>;
						ti,max-div = <0x7f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x210>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x90>;
					};

					dpll_per_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x61>;
						phandle = <0x66>;
					};

					dpll_per_h11x2_ck@158 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x158>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x67>;
					};

					dpll_per_h12x2_ck@15c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x15c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x6b>;
					};

					dpll_per_h13x2_ck@160 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x160>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x7e>;
					};

					dpll_per_h14x2_ck@164 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x164>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x74>;
					};

					dpll_per_m2x2_ck@150 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x150>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x58>;
					};

					dpll_usb_clkdcoldo {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x65>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x6a>;
					};

					func_128m_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x67>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x79>;
					};

					func_12m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x58>;
						clock-mult = <0x1>;
						clock-div = <0x10>;
						phandle = <0x15b>;
					};

					func_24m_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x62>;
						clock-mult = <0x1>;
						clock-div = <0x4>;
						phandle = <0x40>;
					};

					func_48m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x58>;
						clock-mult = <0x1>;
						clock-div = <0x4>;
						phandle = <0x57>;
					};

					func_96m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x58>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x15c>;
					};

					l3init_60m_fclk@104 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x68>;
						reg = <0x104>;
						ti,dividers = <0x1 0x8>;
						phandle = <0x15d>;
					};

					clkout2_clk@6b0 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x69>;
						ti,bit-shift = <0x8>;
						reg = <0x6b0>;
						phandle = <0x132>;
					};

					l3init_960m_gfclk@6c0 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6a>;
						ti,bit-shift = <0x8>;
						reg = <0x6c0>;
						phandle = <0x6f>;
					};

					dss_32khz_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0xb>;
						reg = <0x1120>;
						phandle = <0x15e>;
					};

					dss_48mhz_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x57>;
						ti,bit-shift = <0x9>;
						reg = <0x1120>;
						phandle = <0x113>;
					};

					dss_dss_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6b>;
						ti,bit-shift = <0x8>;
						reg = <0x1120>;
						ti,set-rate-parent;
						phandle = <0x10f>;
					};

					dss_hdmi_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6c>;
						ti,bit-shift = <0xa>;
						reg = <0x1120>;
						phandle = <0x114>;
					};

					dss_video1_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6d>;
						ti,bit-shift = <0xc>;
						reg = <0x1120>;
						phandle = <0x110>;
					};

					dss_video2_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6e>;
						ti,bit-shift = <0xd>;
						reg = <0x1120>;
						phandle = <0x111>;
					};

					gpio2_dbclk@1760 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1760>;
						phandle = <0x15f>;
					};

					gpio3_dbclk@1768 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1768>;
						phandle = <0x160>;
					};

					gpio4_dbclk@1770 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1770>;
						phandle = <0x161>;
					};

					gpio5_dbclk@1778 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1778>;
						phandle = <0x162>;
					};

					gpio6_dbclk@1780 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1780>;
						phandle = <0x163>;
					};

					gpio7_dbclk@1810 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1810>;
						phandle = <0x164>;
					};

					gpio8_dbclk@1818 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1818>;
						phandle = <0x165>;
					};

					mmc1_clk32k@1328 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1328>;
						phandle = <0x166>;
					};

					mmc2_clk32k@1330 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1330>;
						phandle = <0x167>;
					};

					mmc3_clk32k@1820 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1820>;
						phandle = <0x168>;
					};

					mmc4_clk32k@1828 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1828>;
						phandle = <0x169>;
					};

					sata_ref_clk@1388 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x11>;
						ti,bit-shift = <0x8>;
						reg = <0x1388>;
						phandle = <0xe5>;
					};

					usb_otg_ss1_refclk960m@13f0 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6f>;
						ti,bit-shift = <0x8>;
						reg = <0x13f0>;
						phandle = <0xee>;
					};

					usb_otg_ss2_refclk960m@1340 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6f>;
						ti,bit-shift = <0x8>;
						reg = <0x1340>;
						phandle = <0xf1>;
					};

					usb_phy1_always_on_clk32k@640 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x640>;
						phandle = <0xed>;
					};

					usb_phy2_always_on_clk32k@688 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x688>;
						phandle = <0xf0>;
					};

					usb_phy3_always_on_clk32k@698 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x698>;
						phandle = <0xf2>;
					};

					atl_dpll_clk_mux@c00 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x51 0x3a 0x3b 0x30>;
						ti,bit-shift = <0x18>;
						reg = <0xc00>;
						phandle = <0x71>;
					};

					atl_gfclk_mux@c00 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xa 0x70 0x71>;
						ti,bit-shift = <0x1a>;
						reg = <0xc00>;
						phandle = <0x10>;
					};

					rmii_50mhz_clk_mux@13d0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x39 0x72>;
						ti,bit-shift = <0x18>;
						reg = <0x13d0>;
						phandle = <0x16a>;
					};

					gmac_rft_clk_mux@13d0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3a 0x3b 0x70 0x30 0xa>;
						ti,bit-shift = <0x19>;
						reg = <0x13d0>;
						phandle = <0x10a>;
					};

					gpu_core_gclk_mux@1220 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x73 0x74 0x28>;
						ti,bit-shift = <0x18>;
						reg = <0x1220>;
						assigned-clocks = <0x75>;
						assigned-clock-parents = <0x28>;
						phandle = <0x75>;
					};

					gpu_hyd_gclk_mux@1220 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x73 0x74 0x28>;
						ti,bit-shift = <0x1a>;
						reg = <0x1220>;
						assigned-clocks = <0x76>;
						assigned-clock-parents = <0x28>;
						phandle = <0x76>;
					};

					l3instr_ts_gclk_div@e50 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x77>;
						ti,bit-shift = <0x18>;
						reg = <0xe50>;
						ti,dividers = <0x8 0x10 0x20>;
						phandle = <0x16b>;
					};

					mcasp2_ahclkr_mux@1860 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x1c>;
						reg = <0x1860>;
						phandle = <0xfd>;
					};

					mcasp2_ahclkx_mux@1860 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1860>;
						phandle = <0xfc>;
					};

					mcasp2_aux_gfclk_mux@1860 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1860>;
						phandle = <0xfb>;
					};

					mcasp3_ahclkx_mux@1868 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1868>;
						assigned-clocks = <0x78>;
						assigned-clock-parents = <0x3e>;
						phandle = <0x78>;
					};

					mcasp3_aux_gfclk_mux@1868 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1868>;
						phandle = <0xfe>;
					};

					mcasp4_ahclkx_mux@1898 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1898>;
						phandle = <0x100>;
					};

					mcasp4_aux_gfclk_mux@1898 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1898>;
						phandle = <0xff>;
					};

					mcasp5_ahclkx_mux@1878 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1878>;
						phandle = <0x102>;
					};

					mcasp5_aux_gfclk_mux@1878 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1878>;
						phandle = <0x101>;
					};

					mcasp6_ahclkx_mux@1904 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1904>;
						phandle = <0x104>;
					};

					mcasp6_aux_gfclk_mux@1904 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1904>;
						phandle = <0x103>;
					};

					mcasp7_ahclkx_mux@1908 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1908>;
						phandle = <0x106>;
					};

					mcasp7_aux_gfclk_mux@1908 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1908>;
						phandle = <0x105>;
					};

					mcasp8_ahclkx_mux@1890 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x16>;
						reg = <0x1890>;
						phandle = <0x108>;
					};

					mcasp8_aux_gfclk_mux@1890 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x18>;
						reg = <0x1890>;
						phandle = <0x107>;
					};

					mmc1_fclk_mux@1328 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x79 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1328>;
						phandle = <0x7a>;
					};

					mmc1_fclk_div@1328 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7a>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1328>;
						ti,index-power-of-two;
						phandle = <0x16c>;
					};

					mmc2_fclk_mux@1330 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x79 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1330>;
						phandle = <0x7b>;
					};

					mmc2_fclk_div@1330 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7b>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1330>;
						ti,index-power-of-two;
						phandle = <0x16d>;
					};

					mmc3_gfclk_mux@1820 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1820>;
						phandle = <0x7c>;
					};

					mmc3_gfclk_div@1820 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7c>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1820>;
						ti,index-power-of-two;
						phandle = <0x16e>;
					};

					mmc4_gfclk_mux@1828 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1828>;
						phandle = <0x7d>;
					};

					mmc4_gfclk_div@1828 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7d>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1828>;
						ti,index-power-of-two;
						phandle = <0x16f>;
					};

					qspi_gfclk_mux@1838 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x79 0x7e>;
						ti,bit-shift = <0x18>;
						reg = <0x1838>;
						phandle = <0x7f>;
					};

					qspi_gfclk_div@1838 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7f>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1838>;
						ti,index-power-of-two;
						phandle = <0xe4>;
					};

					timer10_gfclk_mux@1728 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1728>;
						phandle = <0x170>;
					};

					timer11_gfclk_mux@1730 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1730>;
						phandle = <0x171>;
					};

					timer13_gfclk_mux@17c8 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x17c8>;
						phandle = <0x172>;
					};

					timer14_gfclk_mux@17d0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x17d0>;
						phandle = <0x173>;
					};

					timer15_gfclk_mux@17d8 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x17d8>;
						phandle = <0x174>;
					};

					timer16_gfclk_mux@1830 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1830>;
						assigned-clocks = <0x80>;
						assigned-clock-parents = <0x52>;
						phandle = <0x80>;
					};

					timer2_gfclk_mux@1738 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1738>;
						phandle = <0x175>;
					};

					timer3_gfclk_mux@1740 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1740>;
						phandle = <0x176>;
					};

					timer4_gfclk_mux@1748 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1748>;
						phandle = <0x177>;
					};

					timer9_gfclk_mux@1750 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1750>;
						phandle = <0x178>;
					};

					uart1_gfclk_mux@1840 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1840>;
						phandle = <0x179>;
					};

					uart2_gfclk_mux@1848 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1848>;
						phandle = <0x17a>;
					};

					uart3_gfclk_mux@1850 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1850>;
						phandle = <0x17b>;
					};

					uart4_gfclk_mux@1858 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1858>;
						phandle = <0x17c>;
					};

					uart5_gfclk_mux@1870 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1870>;
						phandle = <0x17d>;
					};

					uart7_gfclk_mux@18d0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x18d0>;
						phandle = <0x17e>;
					};

					uart8_gfclk_mux@18e0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x18e0>;
						phandle = <0x17f>;
					};

					uart9_gfclk_mux@18e8 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x18e8>;
						phandle = <0x180>;
					};

					vip1_gclk_mux@1020 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xa 0x81>;
						ti,bit-shift = <0x18>;
						reg = <0x1020>;
						phandle = <0x181>;
					};

					vip2_gclk_mux@1028 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xa 0x81>;
						ti,bit-shift = <0x18>;
						reg = <0x1028>;
						phandle = <0x182>;
					};

					vip3_gclk_mux@1030 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xa 0x81>;
						ti,bit-shift = <0x18>;
						reg = <0x1030>;
						phandle = <0x183>;
					};
				};

				clockdomains {
					phandle = <0x184>;

					coreaon_clkdm {
						compatible = "ti,clockdomain";
						clocks = <0x65>;
						phandle = <0x185>;
					};
				};
			};
		};

		l4@4ae00000 {
			compatible = "ti,dra7-l4-wkup", "simple-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4ae00000 0x3f000>;
			phandle = <0x186>;

			counter@4000 {
				compatible = "ti,omap-counter32k";
				reg = <0x4000 0x40>;
				ti,hwmods = "counter_32k";
				phandle = <0x187>;
			};

			prm@6000 {
				compatible = "ti,dra7-prm";
				reg = <0x6000 0x3000>;
				interrupts = <0x0 0x6 0x4>;
				phandle = <0x188>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					phandle = <0x189>;

					sys_clkin1@110 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x82 0x83 0x84 0x85 0x86 0x87 0x88>;
						reg = <0x110>;
						ti,index-starts-at-one;
						phandle = <0x11>;
					};

					abe_dpll_sys_clk_mux@118 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						reg = <0x118>;
						phandle = <0x89>;
					};

					abe_dpll_bypass_clk_mux@114 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x89 0x51>;
						reg = <0x114>;
						phandle = <0x13>;
					};

					abe_dpll_clk_mux@10c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x89 0x51>;
						reg = <0x10c>;
						phandle = <0x12>;
					};

					abe_24m_fclk@11c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x16>;
						reg = <0x11c>;
						ti,dividers = <0x8 0x10>;
						phandle = <0x3e>;
					};

					aess_fclk@178 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8a>;
						reg = <0x178>;
						ti,max-div = <0x2>;
						phandle = <0x8b>;
					};

					abe_giclk_div@174 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8b>;
						reg = <0x174>;
						ti,max-div = <0x2>;
						phandle = <0x52>;
					};

					abe_lp_clk_div@1d8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x16>;
						reg = <0x1d8>;
						ti,dividers = <0x10 0x20>;
						phandle = <0xaa>;
					};

					abe_sys_clk_div@120 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						reg = <0x120>;
						ti,max-div = <0x2>;
						phandle = <0x3f>;
					};

					adc_gfclk_mux@1dc {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45 0x51>;
						reg = <0x1dc>;
						phandle = <0x18a>;
					};

					sys_clk1_dclk_div@1c8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						ti,max-div = <0x40>;
						reg = <0x1c8>;
						ti,index-power-of-two;
						phandle = <0x93>;
					};

					sys_clk2_dclk_div@1cc {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x45>;
						ti,max-div = <0x40>;
						reg = <0x1cc>;
						ti,index-power-of-two;
						phandle = <0x94>;
					};

					per_abe_x1_dclk_div@1bc {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x70>;
						ti,max-div = <0x40>;
						reg = <0x1bc>;
						ti,index-power-of-two;
						phandle = <0x95>;
					};

					dsp_gclk_div@18c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x21>;
						ti,max-div = <0x40>;
						reg = <0x18c>;
						ti,index-power-of-two;
						phandle = <0x97>;
					};

					gpu_dclk@1a0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x28>;
						ti,max-div = <0x40>;
						reg = <0x1a0>;
						ti,index-power-of-two;
						phandle = <0x99>;
					};

					emif_phy_dclk_div@190 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8c>;
						ti,max-div = <0x40>;
						reg = <0x190>;
						ti,index-power-of-two;
						phandle = <0x9b>;
					};

					gmac_250m_dclk_div@19c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8d>;
						ti,max-div = <0x40>;
						reg = <0x19c>;
						ti,index-power-of-two;
						phandle = <0x8e>;
					};

					gmac_main_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x8e>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x109>;
					};

					l3init_480m_dclk_div@1ac {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x68>;
						ti,max-div = <0x40>;
						reg = <0x1ac>;
						ti,index-power-of-two;
						phandle = <0xa0>;
					};

					usb_otg_dclk_div@184 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8f>;
						ti,max-div = <0x40>;
						reg = <0x184>;
						ti,index-power-of-two;
						phandle = <0xa1>;
					};

					sata_dclk_div@1c0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						ti,max-div = <0x40>;
						reg = <0x1c0>;
						ti,index-power-of-two;
						phandle = <0xa2>;
					};

					pcie2_dclk_div@1b8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x90>;
						ti,max-div = <0x40>;
						reg = <0x1b8>;
						ti,index-power-of-two;
						phandle = <0xa3>;
					};

					pcie_dclk_div@1b4 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x91>;
						ti,max-div = <0x40>;
						reg = <0x1b4>;
						ti,index-power-of-two;
						phandle = <0xa4>;
					};

					emu_dclk_div@194 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						ti,max-div = <0x40>;
						reg = <0x194>;
						ti,index-power-of-two;
						phandle = <0xa5>;
					};

					secure_32k_dclk_div@1c4 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x92>;
						ti,max-div = <0x40>;
						reg = <0x1c4>;
						ti,index-power-of-two;
						phandle = <0xa6>;
					};

					clkoutmux0_clk_mux@158 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
						reg = <0x158>;
						phandle = <0x56>;
					};

					clkoutmux1_clk_mux@15c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
						reg = <0x15c>;
						phandle = <0x18b>;
					};

					clkoutmux2_clk_mux@160 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
						reg = <0x160>;
						phandle = <0x69>;
					};

					custefuse_sys_gfclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x11>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x18c>;
					};

					eve_clk@180 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x34 0x37>;
						reg = <0x180>;
						phandle = <0x18d>;
					};

					hdmi_dpll_clk_mux@164 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						reg = <0x164>;
						phandle = <0x6c>;
					};

					mlb_clk@134 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xa8>;
						ti,max-div = <0x40>;
						reg = <0x134>;
						ti,index-power-of-two;
						phandle = <0x4a>;
					};

					mlbp_clk@130 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xa9>;
						ti,max-div = <0x40>;
						reg = <0x130>;
						ti,index-power-of-two;
						phandle = <0x4b>;
					};

					per_abe_x1_gfclk2_div@138 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x70>;
						ti,max-div = <0x40>;
						reg = <0x138>;
						ti,index-power-of-two;
						phandle = <0x4c>;
					};

					timer_sys_clk_div@144 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						reg = <0x144>;
						ti,max-div = <0x2>;
						phandle = <0x50>;
					};

					video1_dpll_clk_mux@168 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						reg = <0x168>;
						phandle = <0x6d>;
					};

					video2_dpll_clk_mux@16c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						reg = <0x16c>;
						phandle = <0x6e>;
					};

					wkupaon_iclk_mux@108 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0xaa>;
						reg = <0x108>;
						phandle = <0x77>;
					};

					gpio1_dbclk@1838 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1838>;
						phandle = <0x18e>;
					};

					dcan1_sys_clk_mux@1888 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						ti,bit-shift = <0x18>;
						reg = <0x1888>;
						phandle = <0x10d>;
					};

					timer1_gfclk_mux@1840 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1840>;
						phandle = <0x18f>;
					};

					uart10_gfclk_mux@1880 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1880>;
						phandle = <0x190>;
					};
				};

				clockdomains {
					phandle = <0x191>;
				};
			};

			scm_conf@c000 {
				compatible = "syscon";
				reg = <0xc000 0x1000>;
				phandle = <0x7>;
			};
		};

		axi@0 {
			compatible = "simple-bus";
			#size-cells = <0x1>;
			#address-cells = <0x1>;
			ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>;

			pcie@51000000 {
				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
				reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>;
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				device_type = "pci";
				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>;
				bus-range = <0x0 0xff>;
				#interrupt-cells = <0x1>;
				num-lanes = <0x1>;
				linux,pci-domain = <0x0>;
				ti,hwmods = "pcie1";
				phys = <0xab>;
				phy-names = "pcie-phy0";
				ti,syscon-conf = <0x9>;
				ti,syscon-pcie = <0xac>;
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0xad 0x1 0x0 0x0 0x0 0x2 0xad 0x2 0x0 0x0 0x0 0x3 0xad 0x3 0x0 0x0 0x0 0x4 0xad 0x4>;
				ti,syscon-unaligned-access = <0xae 0x14 0x1>;
				status = "ok";
				gpios = <0xaf 0x8 0x1>;
				phandle = <0x192>;

				interrupt-controller {
					interrupt-controller;
					#address-cells = <0x0>;
					#interrupt-cells = <0x1>;
					phandle = <0xad>;
				};
			};

			pcie_ep@51000000 {
				compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
				reg = <0x51000000 0x28 0x51002000 0x14c 0x51001000 0x28 0x1000 0x10000000>;
				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
				interrupts = <0x0 0xe8 0x4>;
				num-lanes = <0x1>;
				num-ib-windows = <0x4>;
				num-ob-windows = <0x10>;
				ti,hwmods = "pcie1";
				phys = <0xab>;
				phy-names = "pcie-phy0";
				ti,syscon-unaligned-access = <0xae 0x14 0x1>;
				ti,syscon-conf = <0x9>;
				ti,syscon-pcie = <0xac>;
				status = "disabled";
				gpios = <0xaf 0x8 0x1>;
				phandle = <0x193>;
			};
		};

		axi@1 {
			compatible = "simple-bus";
			#size-cells = <0x1>;
			#address-cells = <0x1>;
			ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>;
			status = "disabled";

			pcie@51800000 {
				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
				reg = <0x51800000 0x2000 0x51802000 0x14c 0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0x0 0x163 0x4 0x0 0x164 0x4>;
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				device_type = "pci";
				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x30013000 0x13000 0x0 0xffed000>;
				bus-range = <0x0 0xff>;
				#interrupt-cells = <0x1>;
				num-lanes = <0x1>;
				linux,pci-domain = <0x1>;
				ti,hwmods = "pcie2";
				phys = <0xb0>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0xb1 0x1 0x0 0x0 0x0 0x2 0xb1 0x2 0x0 0x0 0x0 0x3 0xb1 0x3 0x0 0x0 0x0 0x4 0xb1 0x4>;
				ti,syscon-unaligned-access = <0xae 0x14 0x2>;
				phandle = <0x194>;

				interrupt-controller {
					interrupt-controller;
					#address-cells = <0x0>;
					#interrupt-cells = <0x1>;
					phandle = <0xb1>;
				};
			};
		};

		ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x80000>;
			ranges = <0x0 0x40300000 0x80000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			phandle = <0x195>;

			sram-hs@0 {
				compatible = "ti,secure-ram";
				reg = <0x0 0x0>;
			};
		};

		ocmcram@40400000 {
			status = "disabled";
			compatible = "mmio-sram";
			reg = <0x40400000 0x100000>;
			ranges = <0x0 0x40400000 0x100000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			phandle = <0x196>;
		};

		ocmcram@40500000 {
			status = "disabled";
			compatible = "mmio-sram";
			reg = <0x40500000 0x100000>;
			ranges = <0x0 0x40500000 0x100000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			phandle = <0x197>;
		};

		bandgap@4a0021e0 {
			reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x8 0x4a002574 0x50>;
			compatible = "ti,dra752-bandgap";
			interrupts = <0x0 0x79 0x4>;
			#thermal-sensor-cells = <0x1>;
			phandle = <0x121>;
		};

		dsp_system@40d00000 {
			compatible = "syscon";
			reg = <0x40d00000 0x100>;
			phandle = <0xe0>;
		};

		padconf@4844a000 {
			compatible = "ti,dra7-iodelay";
			reg = <0x4844a000 0xd1c>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			#pinctrl-cells = <0x2>;
			phandle = <0x198>;

			mmc1_iodelay_ddr_rev11_conf {
				pinctrl-pin-array = <0x618 0x23c 0x21c 0x620 0x5f5 0x0 0x624 0x0 0x258 0x628 0x0 0x0 0x62c 0x37 0x0 0x630 0x193 0x78 0x634 0x0 0x0 0x638 0x0 0x0 0x63c 0x17 0x3c 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x19 0x3c 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
				phandle = <0x199>;
			};

			mmc1_iodelay_ddr50_rev20_conf {
				pinctrl-pin-array = <0x618 0x434 0x14a 0x620 0x4f7 0x0 0x624 0x2d2 0x0 0x628 0x0 0x0 0x62c 0x0 0x0 0x630 0x2ef 0x0 0x634 0x0 0x0 0x638 0x14 0x0 0x63c 0x100 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x107 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
				phandle = <0xd9>;
			};

			mmc1_iodelay_sdr104_rev11_conf {
				pinctrl-pin-array = <0x620 0x427 0x11 0x628 0x0 0x0 0x62c 0x17 0x0 0x634 0x0 0x0 0x638 0x0 0x0 0x640 0x0 0x0 0x644 0x2 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
				phandle = <0x19a>;
			};

			mmc1_iodelay_sdr104_rev20_conf {
				pinctrl-pin-array = <0x620 0x258 0x190 0x628 0x0 0x0 0x62c 0x0 0x0 0x634 0x0 0x0 0x638 0x1e 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
				phandle = <0xdb>;
			};

			mmc2_iodelay_hs200_rev11_conf {
				pinctrl-pin-array = <0x190 0x26d 0x258 0x194 0x12c 0x0 0x1a8 0x2e3 0x258 0x1ac 0xf0 0x0 0x1b4 0x32c 0x258 0x1b8 0xf0 0x0 0x1c0 0x3ba 0x258 0x1c4 0x3c 0x0 0x1d0 0x53c 0x1a4 0x1d8 0x3a7 0x258 0x1dc 0x0 0x0 0x1e4 0x20d 0x258 0x1e8 0x78 0x0 0x1f0 0x2ff 0x258 0x1f4 0xe1 0x0 0x1fc 0x235 0x258 0x200 0x3c 0x0 0x364 0x3c9 0x258 0x368 0xb4 0x0>;
				phandle = <0x19b>;
			};

			mmc2_iodelay_hs200_rev20_conf {
				pinctrl-pin-array = <0x190 0x112 0x0 0x194 0xa2 0x0 0x1a8 0x191 0x0 0x1ac 0x49 0x0 0x1b4 0x1d1 0x0 0x1b8 0x73 0x0 0x1c0 0x279 0x0 0x1c4 0x2f 0x0 0x1d0 0x3a7 0x118 0x1d8 0x26d 0x0 0x1dc 0x0 0x0 0x1e4 0xb7 0x0 0x1e8 0x0 0x0 0x1f0 0x1d3 0x0 0x1f4 0x0 0x0 0x1fc 0x106 0x0 0x200 0x2e 0x0 0x364 0x2ac 0x0 0x368 0x4c 0x0>;
				phandle = <0x19c>;
			};

			mmc2_iodelay_ddr_3_3v_rev11_conf {
				pinctrl-pin-array = <0x18c 0x0 0x78 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x109 0x168 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x78 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x78 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x11f 0x1a4 0x1d0 0x36f 0x0 0x1d4 0x90 0xf0 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x78 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x78 0xb4 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
				phandle = <0x19d>;
			};

			mmc2_iodelay_ddr_1_8v_rev11_conf {
				pinctrl-pin-array = <0x18c 0x0 0x0 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x112 0xf0 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x3c 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x3c 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x202 0x168 0x1d0 0x36f 0x0 0x1d4 0xbb 0x78 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x3c 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x79 0x3c 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
				phandle = <0x19e>;
			};

			mmc3_iodelay_manual1_conf {
				pinctrl-pin-array = <0x678 0x196 0x0 0x680 0x293 0x0 0x684 0x0 0x0 0x688 0x0 0x0 0x68c 0x0 0x0 0x690 0x82 0x0 0x694 0x0 0x0 0x698 0x0 0x0 0x69c 0xa9 0x0 0x6a0 0x0 0x0 0x6a4 0x0 0x0 0x6a8 0x0 0x0 0x6ac 0x0 0x0 0x6b0 0x0 0x0 0x6b4 0x1c9 0x0 0x6b8 0x0 0x0 0x6bc 0x0 0x0>;
				phandle = <0x19f>;
			};

			mmc4_iodelay_ds_rev11_conf {
				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x60 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x246 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x187 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x231 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x24c 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
				phandle = <0x1a0>;
			};

			mmc4_iodelay_ds_rev20_conf {
				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x133 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x311 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x265 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x2ab 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x343 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
				phandle = <0x1a1>;
			};

			mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0xa5b 0x0 0x84c 0x624 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x779 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x6b9 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x763 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x77f 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
				phandle = <0x1a2>;
			};

			mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x47b 0x0 0x84c 0x72a 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x875 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x789 0x40 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x78f 0x80 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x87c 0x2c 0x898 0x0 0x0 0x89c 0x0 0x0>;
				phandle = <0x1a3>;
			};
		};

		dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4>;
			#dma-cells = <0x1>;
			dma-channels = <0x20>;
			dma-requests = <0x7f>;
			phandle = <0xe>;
		};

		edma@43300000 {
			compatible = "ti,edma3-tpcc";
			ti,hwmods = "tpcc";
			reg = <0x43300000 0x100000>;
			reg-names = "edma3_cc";
			interrupts = <0x0 0x169 0x4 0x0 0x168 0x4 0x0 0x167 0x4>;
			interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
			dma-requests = <0x40>;
			#dma-cells = <0x2>;
			ti,tptcs = <0xb2 0x7 0xb3 0x0>;
			phandle = <0xf>;
		};

		tptc@43400000 {
			compatible = "ti,edma3-tptc";
			ti,hwmods = "tptc0";
			reg = <0x43400000 0x100000>;
			interrupts = <0x0 0x172 0x4>;
			interrupt-names = "edma3_tcerrint";
			phandle = <0xb2>;
		};

		tptc@43500000 {
			compatible = "ti,edma3-tptc";
			ti,hwmods = "tptc1";
			reg = <0x43500000 0x100000>;
			interrupts = <0x0 0x173 0x4>;
			interrupt-names = "edma3_tcerrint";
			phandle = <0xb3>;
		};

		gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <0x0 0x18 0x4>;
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xcb>;
		};

		gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0x0 0x19 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xaf>;
		};

		gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0x0 0x1a 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x1a4>;
		};

		gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0x0 0x1b 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xcd>;
		};

		gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0x0 0x1c 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x1a5>;
		};

		gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0x0 0x1d 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xd3>;
		};

		gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <0x0 0x1e 0x4>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,no-reset-on-init;
			ti,no-idle-on-init;
			phandle = <0xce>;
		};

		gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <0x0 0x74 0x4>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x1a6>;
		};

		serial@4806a000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts-extended = <0x1 0x0 0x43 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x31 0xb4 0x32>;
			dma-names = "tx", "rx";
			phandle = <0x1a7>;
		};

		serial@4806c000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0x0 0x44 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x33 0xb4 0x34>;
			dma-names = "tx", "rx";
			phandle = <0x1a8>;
		};

		serial@48020000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0x0 0x45 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <0x2dc6c00>;
			status = "okay";
			dmas = <0xb4 0x35 0xb4 0x36>;
			dma-names = "tx", "rx";
			interrupts-extended = <0x1 0x0 0x45 0x4 0xb5 0x3f8>;
			phandle = <0x1a9>;
		};

		serial@4806e000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0x0 0x41 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x37 0xb4 0x38>;
			dma-names = "tx", "rx";
			phandle = <0x1aa>;
		};

		serial@48066000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0x0 0x64 0x4>;
			ti,hwmods = "uart5";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x3f 0xb4 0x40>;
			dma-names = "tx", "rx";
			phandle = <0x1ab>;
		};

		serial@48068000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0x0 0x65 0x4>;
			ti,hwmods = "uart6";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x4f 0xb4 0x50>;
			dma-names = "tx", "rx";
			phandle = <0x1ac>;
		};

		serial@48420000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48420000 0x100>;
			interrupts = <0x0 0xda 0x4>;
			ti,hwmods = "uart7";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			phandle = <0x1ad>;
		};

		serial@48422000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48422000 0x100>;
			interrupts = <0x0 0xdb 0x4>;
			ti,hwmods = "uart8";
			clock-frequency = <0x2dc6c00>;
			status = "okay";
			phandle = <0x1ae>;
		};

		serial@48424000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48424000 0x100>;
			interrupts = <0x0 0xdc 0x4>;
			ti,hwmods = "uart9";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			phandle = <0x1af>;
		};

		serial@4ae2b000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4ae2b000 0x100>;
			interrupts = <0x0 0xdd 0x4>;
			ti,hwmods = "uart10";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			phandle = <0x1b0>;
		};

		mailbox@4a0f4000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4a0f4000 0x200>;
			interrupts = <0x0 0x15 0x4 0x0 0x87 0x4 0x0 0x86 0x4>;
			ti,hwmods = "mailbox1";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x3>;
			ti,mbox-num-fifos = <0x8>;
			status = "disabled";
			phandle = <0x1b1>;
		};

		mailbox@4883a000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883a000 0x200>;
			interrupts = <0x0 0xed 0x4 0x0 0xee 0x4 0x0 0xef 0x4 0x0 0xf0 0x4>;
			ti,hwmods = "mailbox2";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b2>;
		};

		mailbox@4883c000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883c000 0x200>;
			interrupts = <0x0 0xf1 0x4 0x0 0xf2 0x4 0x0 0xf3 0x4 0x0 0xf4 0x4>;
			ti,hwmods = "mailbox3";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b3>;
		};

		mailbox@4883e000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883e000 0x200>;
			interrupts = <0x0 0xf5 0x4 0x0 0xf6 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4>;
			ti,hwmods = "mailbox4";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b4>;
		};

		mailbox@48840000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48840000 0x200>;
			interrupts = <0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4>;
			ti,hwmods = "mailbox5";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "okay";
			phandle = <0xb7>;

			mbox_ipu1_ipc3x {
				ti,mbox-tx = <0x6 0x2 0x2>;
				ti,mbox-rx = <0x4 0x2 0x2>;
				status = "okay";
				phandle = <0xb8>;
			};

			mbox_dsp1_ipc3x {
				ti,mbox-tx = <0x5 0x2 0x2>;
				ti,mbox-rx = <0x1 0x2 0x2>;
				status = "okay";
				phandle = <0xc7>;
			};
		};

		mailbox@48842000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48842000 0x200>;
			interrupts = <0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4>;
			ti,hwmods = "mailbox6";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "okay";
			phandle = <0xbf>;

			mbox_ipu2_ipc3x {
				ti,mbox-tx = <0x6 0x2 0x2>;
				ti,mbox-rx = <0x4 0x2 0x2>;
				status = "okay";
				phandle = <0xc0>;
			};

			mbox_dsp2_ipc3x {
				ti,mbox-tx = <0x5 0x2 0x2>;
				ti,mbox-rx = <0x1 0x2 0x2>;
				status = "okay";
				phandle = <0x11d>;
			};
		};

		mailbox@48844000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48844000 0x200>;
			interrupts = <0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4>;
			ti,hwmods = "mailbox7";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b5>;
		};

		mailbox@48846000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48846000 0x200>;
			interrupts = <0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4>;
			ti,hwmods = "mailbox8";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b6>;
		};

		mailbox@4885e000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4885e000 0x200>;
			interrupts = <0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4>;
			ti,hwmods = "mailbox9";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b7>;
		};

		mailbox@48860000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48860000 0x200>;
			interrupts = <0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4 0x0 0x110 0x4>;
			ti,hwmods = "mailbox10";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b8>;
		};

		mailbox@48862000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48862000 0x200>;
			interrupts = <0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>;
			ti,hwmods = "mailbox11";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b9>;
		};

		mailbox@48864000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48864000 0x200>;
			interrupts = <0x0 0x115 0x4 0x0 0x116 0x4 0x0 0x117 0x4 0x0 0x118 0x4>;
			ti,hwmods = "mailbox12";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1ba>;
		};

		mailbox@48802000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48802000 0x200>;
			interrupts = <0x0 0x17b 0x4 0x0 0x17c 0x4 0x0 0x17d 0x4 0x0 0x17e 0x4>;
			ti,hwmods = "mailbox13";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1bb>;
		};

		timer@4ae18000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <0x0 0x20 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
			phandle = <0x1bc>;
		};

		timer@48032000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0x0 0x21 0x4>;
			ti,hwmods = "timer2";
			phandle = <0x1bd>;
		};

		timer@48034000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0x0 0x22 0x4>;
			ti,hwmods = "timer3";
			phandle = <0xc1>;
		};

		timer@48036000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0x0 0x23 0x4>;
			ti,hwmods = "timer4";
			phandle = <0xc2>;
		};

		timer@48820000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48820000 0x80>;
			interrupts = <0x0 0x24 0x4>;
			ti,hwmods = "timer5";
			phandle = <0xc8>;
		};

		timer@48822000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48822000 0x80>;
			interrupts = <0x0 0x25 0x4>;
			ti,hwmods = "timer6";
			phandle = <0x11e>;
		};

		timer@48824000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48824000 0x80>;
			interrupts = <0x0 0x26 0x4>;
			ti,hwmods = "timer7";
			phandle = <0xbb>;
		};

		timer@48826000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48826000 0x80>;
			interrupts = <0x0 0x27 0x4>;
			ti,hwmods = "timer8";
			phandle = <0xbc>;
		};

		timer@4803e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0x0 0x28 0x4>;
			ti,hwmods = "timer9";
			phandle = <0xc3>;
		};

		timer@48086000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0x0 0x29 0x4>;
			ti,hwmods = "timer10";
			phandle = <0xc9>;
		};

		timer@48088000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0x0 0x2a 0x4>;
			ti,hwmods = "timer11";
			phandle = <0xb9>;
		};

		timer@4ae20000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae20000 0x80>;
			interrupts = <0x0 0x5a 0x4>;
			ti,hwmods = "timer12";
			ti,timer-alwon;
			ti,timer-secure;
			phandle = <0x1be>;
		};

		timer@48828000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48828000 0x80>;
			interrupts = <0x0 0x153 0x4>;
			ti,hwmods = "timer13";
			phandle = <0x11f>;
		};

		timer@4882a000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882a000 0x80>;
			interrupts = <0x0 0x154 0x4>;
			ti,hwmods = "timer14";
			phandle = <0xba>;
		};

		timer@4882c000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882c000 0x80>;
			interrupts = <0x0 0x155 0x4>;
			ti,hwmods = "timer15";
			phandle = <0x1bf>;
		};

		timer@4882e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882e000 0x80>;
			interrupts = <0x0 0x156 0x4>;
			ti,hwmods = "timer16";
			phandle = <0x1c0>;
		};

		wdt@4ae14000 {
			compatible = "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <0x0 0x4b 0x4>;
			ti,hwmods = "wd_timer2";
			phandle = <0x1c1>;
		};

		spinlock@4a0f6000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x4a0f6000 0x1000>;
			ti,hwmods = "spinlock";
			#hwlock-cells = <0x1>;
			phandle = <0x1c2>;
		};

		dmm@4e000000 {
			compatible = "ti,dra7-dmm", "ti,omap5-dmm";
			reg = <0x4e000000 0x800>;
			interrupts = <0x0 0x6c 0x4>;
			ti,hwmods = "dmm";
		};

		ipu@58820000 {
			compatible = "ti,dra7-ipu";
			reg = <0x58820000 0x10000>;
			reg-names = "l2ram";
			ti,hwmods = "ipu1";
			iommus = <0xb6>;
			ti,rproc-standby-info = <0x4a005520>;
			status = "okay";
			mboxes = <0xb7 0xb8>;
			timers = <0xb9 0xba>;
			watchdog-timers = <0xbb 0xbc>;
			memory-region = <0xbd>;
			phandle = <0x1c3>;
		};

		ipu@55020000 {
			compatible = "ti,dra7-ipu";
			reg = <0x55020000 0x10000>;
			reg-names = "l2ram";
			ti,hwmods = "ipu2";
			iommus = <0xbe>;
			ti,rproc-standby-info = <0x4a008920>;
			status = "okay";
			mboxes = <0xbf 0xc0>;
			timers = <0xc1>;
			watchdog-timers = <0xc2 0xc3>;
			memory-region = <0xc4>;
			phandle = <0x1c4>;
		};

		dsp@40800000 {
			compatible = "ti,dra7-dsp";
			reg = <0x40800000 0x48000 0x40e00000 0x8000 0x40f00000 0x8000>;
			reg-names = "l2ram", "l1pram", "l1dram";
			ti,hwmods = "dsp1";
			syscon-bootreg = <0x9 0x55c>;
			iommus = <0xc5 0xc6>;
			ti,rproc-standby-info = <0x4a005420>;
			status = "okay";
			mboxes = <0xb7 0xc7>;
			timers = <0xc8>;
			watchdog-timers = <0xc9>;
			memory-region = <0xca>;
			phandle = <0x1c5>;
		};

		i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0x0 0x33 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c1";
			status = "okay";
			clock-frequency = <0x61a80>;
			phandle = <0x1c6>;

			tps659038@58 {
				status = "disabled";
				compatible = "ti,tps659038";
				reg = <0x58>;
				interrupt-parent = <0xcb>;
				interrupts = <0x0 0x8>;
				#interrupt-cells = <0x2>;
				interrupt-controller;
				ti,system-power-controller;
				ti,palmas-override-powerhold;
				phandle = <0xcc>;

				tps659038_pmic {
					compatible = "ti,tps659038-pmic";

					regulators {

						smps12 {
							regulator-name = "smps12";
							regulator-min-microvolt = <0xcf850>;
							regulator-max-microvolt = <0x1312d0>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x6>;
						};

						smps3 {
							regulator-name = "smps3";
							regulator-min-microvolt = <0x149970>;
							regulator-max-microvolt = <0x149970>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x12a>;
						};

						smps45 {
							regulator-name = "smps45";
							regulator-min-microvolt = <0xcf850>;
							regulator-max-microvolt = <0x1312d0>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1c7>;
						};

						smps6 {
							regulator-name = "smps6";
							regulator-min-microvolt = <0xcf850>;
							regulator-max-microvolt = <0x118c30>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1c8>;
						};

						smps8 {
							regulator-name = "smps8";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x1b7740>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1c9>;
						};

						ldo1 {
							regulator-name = "ldo1";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x325aa0>;
							regulator-boot-on;
							regulator-always-on;
							phandle = <0xdc>;
						};

						ldo2 {
							regulator-name = "ldo2";
							regulator-min-microvolt = <0x325aa0>;
							regulator-max-microvolt = <0x325aa0>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1ca>;
						};

						ldo3 {
							regulator-name = "ldo3";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x1b7740>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1cb>;
						};

						ldo4 {
							regulator-name = "ldo4";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x1b7740>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x115>;
						};

						ldo9 {
							regulator-name = "ldo9";
							regulator-min-microvolt = <0x100590>;
							regulator-max-microvolt = <0x100590>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1cc>;
						};

						ldoln {
							regulator-name = "ldoln";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x1b7740>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x112>;
						};

						ldousb {
							regulator-name = "ldousb";
							regulator-min-microvolt = <0x325aa0>;
							regulator-max-microvolt = <0x325aa0>;
							regulator-boot-on;
							phandle = <0xef>;
						};

						regen1 {
							regulator-name = "regen1";
							regulator-boot-on;
							regulator-always-on;
							phandle = <0x129>;
						};
					};
				};

				tps659038_rtc {
					compatible = "ti,palmas-rtc";
					interrupt-parent = <0xcc>;
					interrupts = <0x8 0x2>;
					wakeup-source;
					phandle = <0x1cd>;
				};

				tps659038_pwr_button {
					compatible = "ti,palmas-pwrbutton";
					interrupt-parent = <0xcc>;
					interrupts = <0x1 0x2>;
					wakeup-source;
					ti,palmas-long-press-seconds = <0xc>;
					phandle = <0x1ce>;
				};

				tps659038_gpio {
					compatible = "ti,palmas-gpio";
					gpio-controller;
					#gpio-cells = <0x2>;
					phandle = <0x12b>;
				};

				tps659038_usb {
					compatible = "ti,palmas-usb-vid";
					ti,enable-vbus-detection;
					vbus-gpio = <0xcd 0x15 0x0>;
					phandle = <0xf5>;
				};
			};

			tmp102@48 {
				compatible = "ti,tmp102";
				reg = <0x48>;
				interrupt-parent = <0xce>;
				interrupts = <0x10 0x8>;
				#thermal-sensor-cells = <0x1>;
				phandle = <0x126>;
			};

			tlv320aic3104@18 {
				#sound-dai-cells = <0x0>;
				compatible = "ti,tlv320aic3104";
				reg = <0x18>;
				assigned-clocks = <0x69>;
				assigned-clock-parents = <0x94>;
				status = "okay";
				adc-settle-ms = <0x28>;
				AVDD-supply = <0xcf>;
				IOVDD-supply = <0xcf>;
				DRVDD-supply = <0xcf>;
				DVDD-supply = <0xd0>;
				phandle = <0x131>;
			};

			eeprom@50 {
				compatible = "atmel,24c32";
				reg = <0x50>;
				phandle = <0x1cf>;
			};
		};

		i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0x0 0x34 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c2";
			status = "disabled";
			phandle = <0x1d0>;
		};

		i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0x0 0x38 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c3";
			status = "okay";
			clock-frequency = <0x61a80>;
			phandle = <0x1d1>;

			rtc@6f {
				compatible = "microchip,mcp7941x";
				reg = <0x6f>;
				interrupts-extended = <0x1 0x0 0x2 0x1 0xb5 0x424>;
				interrupt-names = "irq", "wakeup";
				vcc-supply = <0xcf>;
				wakeup-source;
				phandle = <0x1d2>;
			};
		};

		i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <0x0 0x39 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c4";
			status = "disabled";
			phandle = <0x1d3>;
		};

		i2c@4807c000 {
			clock-frequency = <0x61a80>;
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <0x0 0x37 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c5";
			status = "okay";
			phandle = <0x1d4>;

			pixcir_ts@5c {
				touchscreen-size-y = <0x258>;
				touchscreen-size-x = <0x400>;
				reset-gpio = <0xaf 0x6 0x0>;
				reg = <0x5c>;
				interrupts = <0x4 0x0>;
				interrupt-parent = <0xaf>;
				attb-gpio = <0xaf 0x4 0x0>;
				compatible = "pixcir,pixcir_tangoc";
			};
		};

		mmc@4809c000 {
			compatible = "ti,dra7-sdhci";
			reg = <0x4809c000 0x400>;
			interrupts = <0x0 0x4e 0x4>;
			ti,hwmods = "mmc1";
			status = "okay";
			pbias-supply = <0xd1>;
			max-frequency = <0xb71b000>;
			mmc-ddr-1_8v;
			pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
			pinctrl-0 = <0xd2>;
			bus-width = <0x4>;
			cd-gpios = <0xd3 0x1b 0x1>;
			pinctrl-1 = <0xd4>;
			pinctrl-2 = <0xd5>;
			pinctrl-3 = <0xd6>;
			pinctrl-4 = <0xd7>;
			pinctrl-5 = <0xd8 0xd9>;
			pinctrl-6 = <0xda 0xdb>;
			vmmc-supply = <0xcf>;
			vqmmc-supply = <0xdc>;
			phandle = <0x1d5>;
		};

		mmc@480b4000 {
			compatible = "ti,dra7-sdhci";
			reg = <0x480b4000 0x400>;
			interrupts = <0x0 0x51 0x4>;
			ti,hwmods = "mmc2";
			status = "disabled";
			max-frequency = <0xb71b000>;
			sdhci-caps-mask = <0x7 0x0>;
			mmc-hs200-1_8v;
			mmc-ddr-1_8v;
			pinctrl-names = "default", "hs", "ddr_1_8v";
			pinctrl-0 = <0xdd>;
			vmmc-supply = <0xcf>;
			vqmmc-supply = <0xcf>;
			bus-width = <0x8>;
			non-removable;
			no-1-8-v;
			pinctrl-1 = <0xde>;
			pinctrl-2 = <0xdf>;
			phandle = <0x1d6>;
		};

		mmc@480ad000 {
			pinctrl-4 = <0x144 0x19f>;
			pinctrl-3 = <0x143>;
			pinctrl-2 = <0x142>;
			pinctrl-1 = <0x141>;
			pinctrl-0 = <0x140>;
			pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50";
			#size-cells = <0x0>;
			#address-cells = <0x1>;
			non-removable;
			keep-power-in-suspend;
			cap-power-off-card;
			bus-width = <0x4>;
			vqmmc-supply = <0x24a>;
			vmmc-supply = <0x249>;
			compatible = "ti,dra7-sdhci";
			reg = <0x480ad000 0x400>;
			interrupts = <0x0 0x59 0x4>;
			ti,hwmods = "mmc3";
			status = "disabled";
			max-frequency = <0x3d09000>;
			sdhci-caps-mask = <0x0 0x400000>;
			phandle = <0x1d7>;

			wlcore@2 {
				phandle = <0x24c>;
				interrupts = <0x7 0x1>;
				interrupt-parent = <0x1a5>;
				reg = <0x2>;
				compatible = "ti,wl1835";
			};
		};

		mmc@480d1000 {
			compatible = "ti,dra7-sdhci";
			reg = <0x480d1000 0x400>;
			interrupts = <0x0 0x5b 0x4>;
			ti,hwmods = "mmc4";
			status = "disabled";
			max-frequency = <0xb71b000>;
			sdhci-caps-mask = <0x0 0x400000>;
			phandle = <0x1d8>;
		};

		mmu@40d01000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x40d01000 0x100>;
			interrupts = <0x0 0x17 0x4>;
			ti,hwmods = "mmu0_dsp1";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0xe0 0x0>;
			phandle = <0xc5>;
		};

		mmu@40d02000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x40d02000 0x100>;
			interrupts = <0x0 0x91 0x4>;
			ti,hwmods = "mmu1_dsp1";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0xe0 0x1>;
			phandle = <0xc6>;
		};

		mmu@58882000 {
			compatible = "ti,dra7-iommu";
			reg = <0x58882000 0x100>;
			interrupts = <0x0 0x18b 0x4>;
			ti,hwmods = "mmu_ipu1";
			#iommu-cells = <0x0>;
			ti,iommu-bus-err-back;
			phandle = <0xb6>;
		};

		mmu@55082000 {
			compatible = "ti,dra7-iommu";
			reg = <0x55082000 0x100>;
			interrupts = <0x0 0x18c 0x4>;
			ti,hwmods = "mmu_ipu2";
			#iommu-cells = <0x0>;
			ti,iommu-bus-err-back;
			phandle = <0xbe>;
		};

		pruss_soc_bus@4b226004 {
			compatible = "ti,am5728-pruss-soc-bus";
			reg = <0x4b226004 0x4>;
			ti,hwmods = "pruss1";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4b200000 0x80000>;
			status = "okay";
			phandle = <0x1d9>;

			pruss@0 {
				compatible = "ti,am5728-pruss";
				reg = <0x0 0x80000>;
				interrupts = <0x0 0xba 0x4 0x0 0xbb 0x4 0x0 0xbc 0x4 0x0 0xbd 0x4 0x0 0xbe 0x4 0x0 0xbf 0x4 0x0 0xc0 0x4 0x0 0xc1 0x4>;
				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges;
				status = "okay";
				phandle = <0x1da>;

				memories@0 {
					reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x8000 0x2e000 0x31c 0x30000 0x60>;
					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
					phandle = <0x1db>;
				};

				cfg@26000 {
					compatible = "syscon";
					reg = <0x26000 0x2000>;
					phandle = <0x1dc>;
				};

				mii_rt@32000 {
					compatible = "syscon";
					reg = <0x32000 0x58>;
					phandle = <0x1dd>;
				};

				intc@20000 {
					compatible = "ti,am5728-pruss-intc";
					reg = <0x20000 0x2000>;
					reg-names = "intc";
					interrupt-controller;
					#interrupt-cells = <0x1>;
					phandle = <0xe1>;
				};

				pru@34000 {
					compatible = "ti,am5728-pru";
					reg = <0x34000 0x3000 0x22000 0x400 0x22400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am57xx-pru1_0-fw";
					interrupt-parent = <0xe1>;
					interrupts = <0x10 0x11>;
					interrupt-names = "vring", "kick";
					phandle = <0x1de>;
				};

				pru@38000 {
					compatible = "ti,am5728-pru";
					reg = <0x38000 0x3000 0x24000 0x400 0x24400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am57xx-pru1_1-fw";
					interrupt-parent = <0xe1>;
					interrupts = <0x12 0x13>;
					interrupt-names = "vring", "kick";
					phandle = <0x1df>;
				};

				mdio@32400 {
					compatible = "ti,davinci_mdio";
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					clocks = <0xe2>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					reg = <0x32400 0x90>;
					status = "disabled";
					phandle = <0x1e0>;
				};
			};
		};

		pruss_soc_bus@4b2a6004 {
			compatible = "ti,am5728-pruss-soc-bus";
			reg = <0x4b2a6004 0x4>;
			ti,hwmods = "pruss2";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4b280000 0x80000>;
			status = "okay";
			phandle = <0x1e1>;

			pruss@0 {
				compatible = "ti,am5728-pruss";
				reg = <0x0 0x80000>;
				interrupts = <0x0 0xc4 0x4 0x0 0xc5 0x4 0x0 0xc6 0x4 0x0 0xc7 0x4 0x0 0xc8 0x4 0x0 0xc9 0x4 0x0 0xca 0x4 0x0 0xcb 0x4>;
				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges;
				status = "okay";
				phandle = <0x1e2>;

				memories@0 {
					reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x8000 0x2e000 0x31c 0x30000 0x60>;
					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
					phandle = <0x1e3>;
				};

				cfg@26000 {
					compatible = "syscon";
					reg = <0x26000 0x2000>;
					phandle = <0x1e4>;
				};

				iep@2e000 {
					compatible = "syscon";
					reg = <0x2e000 0x31c>;
					phandle = <0x1e5>;
				};

				mii_rt@32000 {
					compatible = "syscon";
					reg = <0x32000 0x58>;
					phandle = <0x1e6>;
				};

				intc@20000 {
					compatible = "ti,am5728-pruss-intc";
					reg = <0x20000 0x2000>;
					reg-names = "intc";
					interrupt-controller;
					#interrupt-cells = <0x1>;
					phandle = <0xe3>;
				};

				pru@34000 {
					compatible = "ti,am5728-pru";
					reg = <0x34000 0x3000 0x22000 0x400 0x22400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am57xx-pru2_0-fw";
					interrupt-parent = <0xe3>;
					interrupts = <0x10 0x11>;
					interrupt-names = "vring", "kick";
					phandle = <0x1e7>;
				};

				pru@38000 {
					compatible = "ti,am5728-pru";
					reg = <0x38000 0x3000 0x24000 0x400 0x24400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am57xx-pru2_1-fw";
					interrupt-parent = <0xe3>;
					interrupts = <0x12 0x13>;
					interrupt-names = "vring", "kick";
					phandle = <0x1e8>;
				};

				mdio@32400 {
					compatible = "ti,davinci_mdio";
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					clocks = <0xe2>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					reg = <0x32400 0x90>;
					status = "disabled";
					phandle = <0x1e9>;
				};
			};
		};

		regulator-abb-mpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_mpu";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0x11>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07ddc 0x4 0x4ae07de0 0x4 0x4ae06014 0x4 0x4a003b20 0xc 0x4ae0c158 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x102ca0 0x0 0x0 0x0 0x2000000 0x1f00000 0x11b340 0x0 0x4 0x0 0x2000000 0x1f00000 0x127690 0x0 0x8 0x0 0x2000000 0x1f00000>;
			phandle = <0x5>;
		};

		regulator-abb-ivahd {
			compatible = "ti,abb-v3";
			regulator-name = "abb_ivahd";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0x11>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07e34 0x4 0x4ae07e24 0x4 0x4ae06010 0x4 0x4a0025cc 0xc 0x4a002470 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x40000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
			phandle = <0x1ea>;
		};

		regulator-abb-dspeve {
			compatible = "ti,abb-v3";
			regulator-name = "abb_dspeve";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0x11>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07e30 0x4 0x4ae07e20 0x4 0x4ae06010 0x4 0x4a0025e0 0xc 0x4a00246c 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x20000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
			phandle = <0x1eb>;
		};

		regulator-abb-gpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_gpu";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0x11>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07de4 0x4 0x4ae07de8 0x4 0x4ae06010 0x4 0x4a003b08 0xc 0x4ae0c154 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x10000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x10a1d0 0x0 0x0 0x0 0x2000000 0x1f00000 0x127690 0x0 0x4 0x0 0x2000000 0x1f00000 0x138800 0x0 0x8 0x0 0x2000000 0x1f00000>;
			phandle = <0x1ec>;
		};

		spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <0x0 0x3c 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <0x4>;
			dmas = <0xb4 0x23 0xb4 0x24 0xb4 0x25 0xb4 0x26 0xb4 0x27 0xb4 0x28 0xb4 0x29 0xb4 0x2a>;
			dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
			status = "disabled";
			phandle = <0x1ed>;
		};

		spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <0x0 0x3d 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <0x2>;
			dmas = <0xb4 0x2b 0xb4 0x2c 0xb4 0x2d 0xb4 0x2e>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
			status = "disabled";
			phandle = <0x1ee>;
		};

		spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <0x0 0x56 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <0x2>;
			dmas = <0xb4 0xf 0xb4 0x10>;
			dma-names = "tx0", "rx0";
			status = "disabled";
			phandle = <0x1ef>;
		};

		spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <0x0 0x2b 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <0x1>;
			dmas = <0xb4 0x46 0xb4 0x47>;
			dma-names = "tx0", "rx0";
			status = "disabled";
			phandle = <0x1f0>;
		};

		qspi@4b300000 {
			compatible = "ti,dra7xxx-qspi";
			reg = <0x4b300000 0x100 0x5c000000 0x4000000>;
			reg-names = "qspi_base", "qspi_mmap";
			syscon-chipselects = <0x9 0x558>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "qspi";
			clocks = <0xe4>;
			clock-names = "fck";
			num-cs = <0x4>;
			interrupts = <0x0 0x157 0x4>;
			status = "disabled";
			phandle = <0x1f1>;
		};

		ocp2scp@4a090000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x4a090000 0x20>;
			ti,hwmods = "ocp2scp3";

			phy@4A096000 {
				compatible = "ti,phy-pipe3-sata";
				reg = <0x4a096000 0x80 0x4a096400 0x64 0x4a096800 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				syscon-phy-power = <0x9 0x374>;
				clocks = <0x11 0xe5>;
				clock-names = "sysclk", "refclk";
				syscon-pllreset = <0x9 0x3fc>;
				#phy-cells = <0x0>;
				phandle = <0xec>;
			};

			pciephy@4a094000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a094000 0x80 0x4a094400 0x64>;
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <0xac 0x1c>;
				syscon-pcs = <0xac 0x10>;
				clocks = <0x59 0x5a 0xe6 0xe7 0xe8 0x5e 0x11>;
				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
				#phy-cells = <0x0>;
				phandle = <0xab>;
			};

			pciephy@4a095000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a095000 0x80 0x4a095400 0x64>;
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <0xac 0x20>;
				syscon-pcs = <0xac 0x10>;
				clocks = <0x59 0x5a 0xe9 0xea 0xeb 0x5e 0x11>;
				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
				#phy-cells = <0x0>;
				status = "disabled";
				phandle = <0xb0>;
			};
		};

		sata@4a141100 {
			compatible = "snps,dwc-ahci";
			reg = <0x4a140000 0x1100 0x4a141100 0x7>;
			interrupts = <0x0 0x31 0x4>;
			phys = <0xec>;
			phy-names = "sata-phy";
			clocks = <0xe5>;
			ti,hwmods = "sata";
			ports-implemented = <0x1>;
			status = "okay";
			phandle = <0x1f2>;
		};

		rtc@48838000 {
			compatible = "ti,am3352-rtc";
			reg = <0x48838000 0x100>;
			interrupts = <0x0 0xd9 0x4 0x0 0xd9 0x4>;
			ti,hwmods = "rtcss";
			clocks = <0x51>;
			phandle = <0x1f3>;
		};

		ocp2scp@4a080000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x4a080000 0x20>;
			ti,hwmods = "ocp2scp1";

			phy@4a084000 {
				compatible = "ti,dra7x-usb2", "ti,omap-usb2";
				reg = <0x4a084000 0x400>;
				syscon-phy-power = <0x9 0x300>;
				clocks = <0xed 0xee>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0x0>;
				phy-supply = <0xef>;
				phandle = <0xf3>;
			};

			phy@4a085000 {
				compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2";
				reg = <0x4a085000 0x400>;
				syscon-phy-power = <0x9 0xe74>;
				clocks = <0xf0 0xf1>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0x0>;
				phy-supply = <0xef>;
				phandle = <0xf6>;
			};

			phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80 0x4a084800 0x64 0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				syscon-phy-power = <0x9 0x370>;
				clocks = <0xf2 0x11 0xee>;
				clock-names = "wkupclk", "sysclk", "refclk";
				#phy-cells = <0x0>;
				phandle = <0xf4>;
			};
		};

		omap_dwc3_1@48880000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss1";
			reg = <0x48880000 0x10000>;
			interrupts = <0x0 0x48 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			phandle = <0x1f4>;

			usb@48890000 {
				compatible = "snps,dwc3";
				reg = <0x48890000 0x17000>;
				interrupts = <0x0 0x47 0x4 0x0 0x47 0x4 0x0 0x48 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				phys = <0xf3 0xf4>;
				phy-names = "usb2-phy", "usb3-phy";
				maximum-speed = "super-speed";
				dr_mode = "host";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
				phandle = <0x1f5>;
			};
		};

		omap_dwc3_2@488c0000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss2";
			reg = <0x488c0000 0x10000>;
			interrupts = <0x0 0x57 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			extcon = <0xf5>;
			phandle = <0x1f6>;

			usb@488d0000 {
				compatible = "snps,dwc3";
				reg = <0x488d0000 0x17000>;
				interrupts = <0x0 0x49 0x4 0x0 0x49 0x4 0x0 0x57 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				phys = <0xf6>;
				phy-names = "usb2-phy";
				maximum-speed = "high-speed";
				dr_mode = "peripheral";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
				snps,dis_metastability_quirk;
				phandle = <0x1f7>;
			};
		};

		omap_dwc3_3@48900000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss3";
			reg = <0x48900000 0x10000>;
			interrupts = <0x0 0x158 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			status = "disabled";
			phandle = <0x1f8>;

			usb@48910000 {
				compatible = "snps,dwc3";
				reg = <0x48910000 0x17000>;
				interrupts = <0x0 0x58 0x4 0x0 0x58 0x4 0x0 0x158 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
				phandle = <0x1f9>;
			};
		};

		elm@48078000 {
			compatible = "ti,am3352-elm";
			reg = <0x48078000 0xfc0>;
			interrupts = <0x0 0x1 0x4>;
			ti,hwmods = "elm";
			status = "disabled";
			phandle = <0x1fa>;
		};

		gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			reg = <0x50000000 0x37c>;
			interrupts = <0x0 0xf 0x4>;
			dmas = <0xf7 0x4 0x0>;
			dma-names = "rxtx";
			gpmc,num-cs = <0x8>;
			gpmc,num-waitpins = <0x2>;
			#address-cells = <0x2>;
			#size-cells = <0x1>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			gpio-controller;
			#gpio-cells = <0x2>;
			status = "disabled";
			phandle = <0x1fb>;
		};

		atl@4843c000 {
			compatible = "ti,dra7-atl";
			reg = <0x4843c000 0x3ff>;
			ti,hwmods = "atl";
			ti,provided-clocks = <0x44 0x43 0x42 0x41>;
			clocks = <0x10>;
			clock-names = "fck";
			status = "disabled";
			phandle = <0x1fc>;
		};

		mcasp@48460000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp1";
			reg = <0x48460000 0x2000 0x45800000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x68 0x4 0x0 0x67 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf7 0x81 0x1 0xf7 0x80 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xf8 0xf9 0xfa>;
			clock-names = "fck", "ahclkx", "ahclkr";
			status = "disabled";
			phandle = <0x1fd>;
		};

		mcasp@48464000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp2";
			reg = <0x48464000 0x2000 0x45c00000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x95 0x4 0x0 0x94 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf7 0x83 0x1 0xf7 0x82 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xfb 0xfc 0xfd>;
			clock-names = "fck", "ahclkx", "ahclkr";
			status = "disabled";
			phandle = <0x1fe>;
		};

		mcasp@48468000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp3";
			reg = <0x48468000 0x2000 0x46000000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x97 0x4 0x0 0x96 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf7 0x85 0x1 0xf7 0x84 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xfe 0x78>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			#sound-dai-cells = <0x0>;
			assigned-clocks = <0x78>;
			assigned-clock-parents = <0x45>;
			op-mode = <0x0>;
			tdm-slots = <0x2>;
			serial-dir = <0x1 0x2 0x0 0x0>;
			tx-num-evt = <0x20>;
			rx-num-evt = <0x20>;
			phandle = <0x130>;
		};

		mcasp@4846c000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp4";
			reg = <0x4846c000 0x2000 0x48436000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x99 0x4 0x0 0x98 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf7 0x87 0x1 0xf7 0x86 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xff 0x100>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x1ff>;
		};

		mcasp@48470000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp5";
			reg = <0x48470000 0x2000 0x4843a000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x9b 0x4 0x0 0x9a 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf7 0x89 0x1 0xf7 0x88 0x1>;
			dma-names = "tx", "rx";
			clocks = <0x101 0x102>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x200>;
		};

		mcasp@48474000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp6";
			reg = <0x48474000 0x2000 0x4844c000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x9d 0x4 0x0 0x9c 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf7 0x8b 0x1 0xf7 0x8a 0x1>;
			dma-names = "tx", "rx";
			clocks = <0x103 0x104>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x201>;
		};

		mcasp@48478000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp7";
			reg = <0x48478000 0x2000 0x48450000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x9f 0x4 0x0 0x9e 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf7 0x8d 0x1 0xf7 0x8c 0x1>;
			dma-names = "tx", "rx";
			clocks = <0x105 0x106>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x202>;
		};

		mcasp@4847c000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp8";
			reg = <0x4847c000 0x2000 0x48454000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0xa1 0x4 0x0 0xa0 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf7 0x8f 0x1 0xf7 0x8e 0x1>;
			dma-names = "tx", "rx";
			clocks = <0x107 0x108>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x203>;
		};

		crossbar@4a002a48 {
			compatible = "ti,irq-crossbar";
			reg = <0x4a002a48 0x130>;
			interrupt-controller;
			interrupt-parent = <0x8>;
			#interrupt-cells = <0x3>;
			ti,max-irqs = <0xa0>;
			ti,max-crossbar-sources = <0x190>;
			ti,reg-size = <0x2>;
			ti,irqs-reserved = <0x0 0x1 0x2 0x3 0x5 0x6 0x83 0x84>;
			ti,irqs-skip = <0xa 0x85 0x8b 0x8c>;
			ti,irqs-safe-map = <0x0>;
			phandle = <0x1>;
		};

		ethernet@48484000 {
			compatible = "ti,dra7-cpsw", "ti,cpsw";
			ti,hwmods = "gmac";
			clocks = <0x109 0x10a>;
			clock-names = "fck", "cpts";
			cpdma_channels = <0x8>;
			ale_entries = <0x400>;
			bd_ram_size = <0x2000>;
			mac_control = <0x20>;
			slaves = <0x2>;
			active_slave = <0x0>;
			cpts_clock_mult = <0x784cfe14>;
			cpts_clock_shift = <0x1d>;
			reg = <0x48484000 0x1000 0x48485200 0x2e00>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ti,no-idle;
			interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>;
			ranges;
			syscon = <0x9>;
			status = "okay";
			dual_emac;
			phandle = <0x204>;

			mdio@48485000 {
				compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <0xf4240>;
				reg = <0x48485000 0x100>;
				phandle = <0x205>;

				ethernet-phy@1 {
					reg = <0x1>;
					phandle = <0x10b>;
				};

				ethernet-phy@2 {
					reg = <0x2>;
					phandle = <0x10c>;
				};
			};

			slave@48480200 {
				mac-address = [00 00 00 00 00 00];
				phy-handle = <0x10b>;
				phy-mode = "rgmii";
				dual_emac_res_vlan = <0x1>;
				phandle = <0x206>;
			};

			slave@48480300 {
				mac-address = [00 00 00 00 00 00];
				phy-handle = <0x10c>;
				phy-mode = "rgmii";
				dual_emac_res_vlan = <0x2>;
				phandle = <0x207>;
			};

			cpsw-phy-sel@4a002554 {
				compatible = "ti,dra7xx-cpsw-phy-sel";
				reg = <0x4a002554 0x4>;
				reg-names = "gmii-sel";
				phandle = <0x208>;
			};
		};

		can@4ae3c000 {
			compatible = "ti,dra7-d_can";
			ti,hwmods = "dcan1";
			reg = <0x4ae3c000 0x2000>;
			syscon-raminit = <0x9 0x558 0x0>;
			interrupts = <0x0 0xde 0x4>;
			clocks = <0x10d>;
			status = "disabled";
			phandle = <0x209>;
		};

		can@48480000 {
			compatible = "ti,dra7-d_can";
			ti,hwmods = "dcan2";
			reg = <0x48480000 0x2000>;
			syscon-raminit = <0x9 0x558 0x1>;
			interrupts = <0x0 0xe1 0x4>;
			clocks = <0x11>;
			status = "disabled";
			phandle = <0x20a>;
		};

		gpu@56000000 {
			compatible = "ti,dra7-sgx544", "img,sgx544";
			reg = <0x56000000 0x10000>;
			reg-names = "gpu_ocp_base";
			interrupts = <0x0 0x10 0x4>;
			ti,hwmods = "gpu";
			clocks = <0xa 0x75 0x76>;
			clock-names = "iclk", "fclk1", "fclk2";
			status = "ok";
			phandle = <0x20b>;
		};

		bb2d@59000000 {
			compatible = "ti,dra7-bb2d";
			reg = <0x59000000 0x700>;
			interrupts = <0x0 0x78 0x4>;
			ti,hwmods = "bb2d";
			clocks = <0x10e>;
			clock-names = "fclk";
			status = "okay";
			phandle = <0x20c>;
		};

		dss@58000000 {
			compatible = "ti,dra7-dss";
			status = "ok";
			ti,hwmods = "dss_core";
			syscon-pll-ctrl = <0x9 0x538>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x58000000 0x80 0x58004054 0x4 0x58004300 0x20 0x58009054 0x4 0x58009300 0x20>;
			reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2";
			clocks = <0x10f 0x110 0x111>;
			clock-names = "fck", "video1_clk", "video2_clk";
			vdda_video-supply = <0x112>;
			phandle = <0x20d>;

			ports {
				#size-cells = <0x0>;
				#address-cells = <0x1>;

				port {
					reg = <0x0>;

					endpoint {
						phandle = <0x247>;
						remote-endpoint = <0x248>;
						data-lines = <0x18>;
					};
				};
			};

			dispc@58001000 {
				compatible = "ti,dra7-dispc";
				reg = <0x58001000 0x1000>;
				interrupts = <0x0 0x14 0x4>;
				ti,hwmods = "dss_dispc";
				clocks = <0x10f>;
				clock-names = "fck";
				syscon-pol = <0x9 0x534>;
			};

			encoder@58060000 {
				compatible = "ti,dra7-hdmi";
				reg = <0x58040000 0x200 0x58040200 0x80 0x58040300 0x80 0x58060000 0x19000>;
				reg-names = "wp", "pll", "phy", "core";
				interrupts = <0x0 0x60 0x4>;
				status = "ok";
				ti,hwmods = "dss_hdmi";
				clocks = <0x113 0x114>;
				clock-names = "fck", "sys_clk";
				dmas = <0xb4 0x4c>;
				dma-names = "audio_tx";
				vdda-supply = <0x115>;
				phandle = <0x20e>;

				port {

					endpoint {
						remote-endpoint = <0x116>;
						phandle = <0x12d>;
					};
				};
			};
		};

		epwmss@4843e000 {
			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
			reg = <0x4843e000 0x30>;
			ti,hwmods = "epwmss0";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "disabled";
			ranges;
			phandle = <0x20f>;

			pwm@4843e200 {
				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x4843e200 0x80>;
				clocks = <0x117 0xb>;
				clock-names = "tbclk", "fck";
				status = "disabled";
				phandle = <0x210>;
			};

			ecap@4843e100 {
				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
				#pwm-cells = <0x3>;
				reg = <0x4843e100 0x80>;
				clocks = <0xb>;
				clock-names = "fck";
				status = "disabled";
				phandle = <0x211>;
			};
		};

		epwmss@48440000 {
			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
			reg = <0x48440000 0x30>;
			ti,hwmods = "epwmss1";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "okay";
			ranges;
			phandle = <0x212>;

			pwm@48440200 {
				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x48440200 0x80>;
				clocks = <0x118 0xb>;
				clock-names = "tbclk", "fck";
				status = "okay";
				phandle = <0x213>;
			};

			ecap@48440100 {
				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
				#pwm-cells = <0x3>;
				reg = <0x48440100 0x80>;
				clocks = <0xb>;
				clock-names = "fck";
				status = "disabled";
				phandle = <0x214>;
			};
		};

		epwmss@48442000 {
			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
			reg = <0x48442000 0x30>;
			ti,hwmods = "epwmss2";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "disabled";
			ranges;
			phandle = <0x215>;

			pwm@48442200 {
				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x48442200 0x80>;
				clocks = <0x119 0xb>;
				clock-names = "tbclk", "fck";
				status = "disabled";
				phandle = <0x216>;
			};

			ecap@48442100 {
				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
				#pwm-cells = <0x3>;
				reg = <0x48442100 0x80>;
				clocks = <0xb>;
				clock-names = "fck";
				status = "disabled";
				phandle = <0x217>;
			};
		};

		aes@4b500000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes1";
			reg = <0x4b500000 0xa0>;
			interrupts = <0x0 0x50 0x4>;
			dmas = <0xf7 0x6f 0x0 0xf7 0x6e 0x0>;
			dma-names = "tx", "rx";
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x218>;
		};

		aes@4b700000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes2";
			reg = <0x4b700000 0xa0>;
			interrupts = <0x0 0x3b 0x4>;
			dmas = <0xf7 0x72 0x0 0xf7 0x71 0x0>;
			dma-names = "tx", "rx";
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x219>;
		};

		des@480a5000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x480a5000 0xa0>;
			interrupts = <0x0 0x4d 0x4>;
			dmas = <0xb4 0x75 0xb4 0x74>;
			dma-names = "tx", "rx";
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x21a>;
		};

		sham@53100000 {
			compatible = "ti,omap5-sham";
			ti,hwmods = "sham";
			reg = <0x4b101000 0x300>;
			interrupts = <0x0 0x2e 0x4>;
			dmas = <0xf7 0x77 0x0>;
			dma-names = "rx";
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x21b>;
		};

		rng@48090000 {
			compatible = "ti,omap4-rng";
			ti,hwmods = "rng";
			reg = <0x48090000 0x2000>;
			interrupts = <0x0 0x2f 0x4>;
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x21c>;
		};

		opp-supply@4a003b20 {
			compatible = "ti,omap5-opp-supply";
			reg = <0x4a003b20 0xc>;
			ti,efuse-settings = <0x102ca0 0x0 0x11b340 0x4 0x127690 0x8>;
			ti,absolute-max-voltage-uv = <0x16e360>;
			phandle = <0x21d>;
		};

		vpe {
			compatible = "ti,vpe";
			ti,hwmods = "vpe";
			clocks = <0x81>;
			clock-names = "fck";
			reg = <0x489d0000 0x120 0x489d0300 0x20 0x489d0400 0x20 0x489d0500 0x20 0x489d0600 0x3c 0x489d0700 0x80 0x489d5700 0x18 0x489dd000 0x400>;
			reg-names = "vpe_top", "vpe_chr_us0", "vpe_chr_us1", "vpe_chr_us2", "vpe_dei", "sc", "csc", "vpdma";
			interrupts = <0x0 0x162 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		vip@0x48970000 {
			compatible = "ti,vip1";
			reg = <0x48970000 0x114 0x48975500 0xd8 0x48975700 0x18 0x48975800 0x80 0x48975a00 0xd8 0x48975c00 0x18 0x48975d00 0x80 0x4897d000 0x400>;
			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
			ti,hwmods = "vip1";
			interrupts = <0x0 0x15f 0x4 0x0 0x188 0x4>;
			syscon-pol = <0x9 0x534>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
			phandle = <0x21e>;

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
				phandle = <0x21f>;
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
				phandle = <0x220>;
			};

			port@2 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x2>;
				status = "disabled";
				phandle = <0x221>;
			};

			port@3 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x3>;
				status = "disabled";
				phandle = <0x222>;
			};
		};

		dsp_system@41500000 {
			compatible = "syscon";
			reg = <0x41500000 0x100>;
			phandle = <0x11a>;
		};

		omap_dwc3_4@48940000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss4";
			reg = <0x48940000 0x10000>;
			interrupts = <0x0 0x15a 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			status = "disabled";
			phandle = <0x223>;

			usb@48950000 {
				compatible = "snps,dwc3";
				reg = <0x48950000 0x17000>;
				interrupts = <0x0 0x159 0x4 0x0 0x159 0x4 0x0 0x15a 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				phandle = <0x224>;
			};
		};

		mmu@41501000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x41501000 0x100>;
			interrupts = <0x0 0x92 0x4>;
			ti,hwmods = "mmu0_dsp2";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0x11a 0x0>;
			phandle = <0x11b>;
		};

		mmu@41502000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x41502000 0x100>;
			interrupts = <0x0 0x93 0x4>;
			ti,hwmods = "mmu1_dsp2";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0x11a 0x1>;
			phandle = <0x11c>;
		};

		dsp@41000000 {
			compatible = "ti,dra7-dsp";
			reg = <0x41000000 0x48000 0x41600000 0x8000 0x41700000 0x8000>;
			reg-names = "l2ram", "l1pram", "l1dram";
			ti,hwmods = "dsp2";
			syscon-bootreg = <0x9 0x560>;
			iommus = <0x11b 0x11c>;
			ti,rproc-standby-info = <0x4a005620>;
			status = "okay";
			mboxes = <0xbf 0x11d>;
			timers = <0x11e>;
			watchdog-timers = <0x11f>;
			memory-region = <0x120>;
			phandle = <0x225>;
		};

		vip@0x48990000 {
			compatible = "ti,vip2";
			reg = <0x48990000 0x114 0x48995500 0xd8 0x48995700 0x18 0x48995800 0x80 0x48995a00 0xd8 0x48995c00 0x18 0x48995d00 0x80 0x4899d000 0x400>;
			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
			ti,hwmods = "vip2";
			interrupts = <0x0 0x160 0x4 0x0 0x189 0x4>;
			syscon-pol = <0x9 0x534>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
			phandle = <0x226>;

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
				phandle = <0x227>;
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
				phandle = <0x228>;
			};

			port@2 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x2>;
				status = "disabled";
				phandle = <0x229>;
			};

			port@3 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x3>;
				status = "disabled";
				phandle = <0x22a>;
			};
		};

		vip@0x489b0000 {
			compatible = "ti,vip3";
			reg = <0x489b0000 0x114 0x489b5500 0xd8 0x489b5700 0x18 0x489b5800 0x80 0x489b5a00 0xd8 0x489b5c00 0x18 0x489b5d00 0x80 0x489bd000 0x400>;
			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
			ti,hwmods = "vip3";
			interrupts = <0x0 0x161 0x4 0x0 0x18a 0x4>;
			syscon-pol = <0x9 0x534>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
			phandle = <0x22b>;

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
				phandle = <0x22c>;
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
				phandle = <0x22d>;
			};
		};
	};

	thermal-zones {
		phandle = <0x22e>;

		cpu_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x121 0x0>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x22f>;

			trips {
				phandle = <0x230>;

				cpu_alert {
					temperature = <0x13880>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x122>;
				};

				cpu_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x231>;
				};

				cpu_alert1 {
					temperature = <0xc350>;
					hysteresis = <0x7d0>;
					type = "active";
					phandle = <0x124>;
				};
			};

			cooling-maps {
				phandle = <0x232>;

				map0 {
					trip = <0x122>;
					cooling-device = <0x123 0xffffffff 0xffffffff>;
				};

				map1 {
					trip = <0x124>;
					cooling-device = <0x125 0xffffffff 0xffffffff>;
				};
			};
		};

		gpu_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x121 0x1>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x233>;

			trips {

				gpu_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x234>;
				};
			};
		};

		core_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x121 0x2>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x235>;

			trips {

				core_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x236>;
				};
			};
		};

		dspeve_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x121 0x3>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x237>;

			trips {

				dspeve_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x238>;
				};
			};
		};

		iva_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x121 0x4>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x239>;

			trips {

				iva_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x23a>;
				};
			};
		};

		board_thermal {
			polling-delay-passive = <0x4e2>;
			polling-delay = <0x5dc>;
			thermal-sensors = <0x126 0x0>;
			phandle = <0x23b>;

			trips {
				phandle = <0x23c>;

				board_alert {
					temperature = <0x9c40>;
					hysteresis = <0x7d0>;
					type = "active";
					phandle = <0x127>;
				};

				board_crit {
					temperature = <0x19a28>;
					hysteresis = <0x0>;
					type = "critical";
					phandle = <0x23d>;
				};
			};

			cooling-maps {
				phandle = <0x23e>;

				map0 {
					trip = <0x127>;
					cooling-device = <0x125 0xffffffff 0xffffffff>;
				};
			};
		};
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <0x8>;
		interrupts = <0x0 0x83 0x4 0x0 0x84 0x4>;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		ipu2-memory@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
			phandle = <0xc4>;
		};

		dsp1-memory@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
			phandle = <0xca>;
		};

		ipu1-memory@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
			phandle = <0xbd>;
		};

		dsp2-memory@9f000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9f000000 0x0 0x800000>;
			reusable;
			status = "okay";
			phandle = <0x120>;
		};

		cmem_block_mem@a0000000 {
			reg = <0x0 0xa0000000 0x0 0xc000000>;
			no-map;
			status = "okay";
			phandle = <0x133>;
		};

		cmem_block_mem@40500000 {
			reg = <0x0 0x40500000 0x0 0x100000>;
			no-map;
			status = "okay";
			phandle = <0x134>;
		};
	};

	fixedregulator-main_12v0 {
		compatible = "regulator-fixed";
		regulator-name = "main_12v0";
		regulator-min-microvolt = <0xb71b00>;
		regulator-max-microvolt = <0xb71b00>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x128>;
	};

	fixedregulator-evm_5v0 {
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x128>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x23f>;
	};

	fixedregulator-vdd_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vdd_3v3";
		vin-supply = <0x129>;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		phandle = <0xcf>;
	};

	fixedregulator-aic_dvdd {
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd_fixed";
		vin-supply = <0xcf>;
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x1b7740>;
		phandle = <0xd0>;
	};

	fixedregulator-vtt {
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		vin-supply = <0x12a>;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <0xce 0xb 0x0>;
		phandle = <0x240>;
	};

	leds {
		compatible = "gpio-leds";

		led0 {
			label = "beagle-x15:usr0";
			gpios = <0xce 0x9 0x0>;
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};

		led1 {
			label = "beagle-x15:usr1";
			gpios = <0xce 0x8 0x0>;
			linux,default-trigger = "cpu0";
			default-state = "off";
		};

		led2 {
			label = "beagle-x15:usr2";
			gpios = <0xce 0xe 0x0>;
			linux,default-trigger = "mmc0";
			default-state = "off";
		};

		led3 {
			label = "beagle-x15:usr3";
			gpios = <0xce 0xf 0x0>;
			linux,default-trigger = "disk-activity";
			default-state = "off";
		};
	};

	gpio_fan {
		compatible = "gpio-fan";
		gpios = <0x12b 0x2 0x0>;
		gpio-fan,speed-map = <0x0 0x0 0x32c8 0x1>;
		#cooling-cells = <0x2>;
		phandle = <0x125>;
	};

	connector {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = [61 00];
		phandle = <0x241>;

		port {

			endpoint {
				remote-endpoint = <0x12c>;
				phandle = <0x12e>;
			};
		};
	};

	encoder {
		compatible = "ti,tpd12s015";
		gpios = <0xce 0xa 0x0 0xaf 0x1e 0x0 0xce 0xc 0x0>;
		phandle = <0x242>;

		ports {
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			port@0 {
				reg = <0x0>;

				endpoint {
					remote-endpoint = <0x12d>;
					phandle = <0x116>;
				};
			};

			port@1 {
				reg = <0x1>;

				endpoint {
					remote-endpoint = <0x12e>;
					phandle = <0x12c>;
				};
			};
		};
	};

	sound0 {
		status = "disabled";
		compatible = "simple-audio-card";
		simple-audio-card,name = "BeagleBoard-X15";
		simple-audio-card,widgets = "Line", "Line Out", "Line", "Line In";
		simple-audio-card,routing = "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC2L", "Line In", "MIC2R", "Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <0x12f>;
		simple-audio-card,frame-master = <0x12f>;
		simple-audio-card,bitclock-inversion;
		phandle = <0x243>;

		simple-audio-card,cpu {
			sound-dai = <0x130>;
			status = "disabled";
		};

		simple-audio-card,codec {
			sound-dai = <0x131>;
			clocks = <0x132>;
			phandle = <0x12f>;
		};
	};

	cmem {
		compatible = "ti,cmem";
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		#pool-size-cells = <0x2>;
		status = "okay";

		cmem_block@0 {
			reg = <0x0>;
			memory-region = <0x133>;
			cmem-buf-pools = <0x1 0x0 0xc000000>;
			phandle = <0x244>;
		};

		cmem_block@1 {
			reg = <0x1>;
			memory-region = <0x134>;
			phandle = <0x245>;
		};
	};

	__symbols__ {
		wlcore = "/ocp/mmc@480ad000/wlcore@2", "";
		dpi_out = "/ocp/dss@58000000/ports/port/endpoint", "";
		vmmcwl_fixed = "/fixedregulator-mmcwl", "";
		com_3v6 = "/fixedregulator-com_3v6", "";
		lcd_bl = "/backlight", "";
		lcd_in = "/display/port/endpoint", "";
		lcd0 = "/display", "";
		gic = "/interrupt-controller@48211000";
		wakeupgen = "/interrupt-controller@48281000";
		cpu0 = "/cpus/cpu@0";
		cpu0_opp_table = "/opp-table";
		l4_cfg = "/ocp/l4@4a000000";
		scm = "/ocp/l4@4a000000/scm@2000";
		scm_conf = "/ocp/l4@4a000000/scm@2000/scm_conf@0";
		pbias_regulator = "/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00";
		pbias_mmc_reg = "/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5";
		scm_conf_clocks = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks";
		dss_deshdcp_clk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dss_deshdcp_clk@558";
		ehrpwm0_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm0_tbclk@558";
		ehrpwm1_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm1_tbclk@558";
		ehrpwm2_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm2_tbclk@558";
		sys_32k_ck = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/sys_32k_ck";
		dra7_pmx_core = "/ocp/l4@4a000000/scm@2000/pinmux@1400";
		mmc1_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default";
		mmc1_pins_default_no_clk_pu = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default_no_clk_pu";
		mmc1_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr12";
		mmc1_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_hs";
		mmc1_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr25";
		mmc1_pins_sdr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr50";
		mmc1_pins_ddr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_ddr50";
		mmc1_pins_sdr104 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr104";
		mmc2_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_default";
		mmc2_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs";
		mmc2_pins_ddr_3_3v_rev11 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_3_3v_rev11";
		mmc2_pins_ddr_1_8v_rev11 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_1_8v_rev11";
		mmc2_pins_ddr_rev20 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_rev20";
		mmc2_pins_hs200 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs200";
		mmc4_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_default";
		mmc4_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_hs";
		mmc3_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_default";
		mmc3_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_hs";
		mmc3_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr12";
		mmc3_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr25";
		mmc3_pins_sdr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr50";
		mmc4_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr12";
		mmc4_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr25";
		scm_conf1 = "/ocp/l4@4a000000/scm@2000/scm_conf@1c04";
		scm_conf_pcie = "/ocp/l4@4a000000/scm@2000/scm_conf@1c24";
		sdma_xbar = "/ocp/l4@4a000000/scm@2000/dma-router@b78";
		edma_xbar = "/ocp/l4@4a000000/scm@2000/dma-router@c78";
		cm_core_aon = "/ocp/l4@4a000000/cm_core_aon@5000";
		cm_core_aon_clocks = "/ocp/l4@4a000000/cm_core_aon@5000/clocks";
		atl_clkin0_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin0_ck";
		atl_clkin1_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin1_ck";
		atl_clkin2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin2_ck";
		atl_clkin3_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin3_ck";
		hdmi_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clkin_ck";
		mlb_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlb_clkin_ck";
		mlbp_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlbp_clkin_ck";
		pciesref_acs_clk_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/pciesref_acs_clk_ck";
		ref_clkin0_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin0_ck";
		ref_clkin1_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin1_ck";
		ref_clkin2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin2_ck";
		ref_clkin3_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin3_ck";
		rmii_clk_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/rmii_clk_ck";
		sdvenc_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sdvenc_clkin_ck";
		secure_32k_clk_src_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/secure_32k_clk_src_ck";
		sys_clk32_crystal_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_crystal_ck";
		sys_clk32_pseudo_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_pseudo_ck";
		virt_12000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_12000000_ck";
		virt_13000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_13000000_ck";
		virt_16800000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_16800000_ck";
		virt_19200000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_19200000_ck";
		virt_20000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_20000000_ck";
		virt_26000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_26000000_ck";
		virt_27000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_27000000_ck";
		virt_38400000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_38400000_ck";
		sys_clkin2 = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clkin2";
		usb_otg_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_otg_clkin_ck";
		video1_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clkin_ck";
		video1_m2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_m2_clkin_ck";
		video2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clkin_ck";
		video2_m2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_m2_clkin_ck";
		dpll_abe_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_ck@1e0";
		dpll_abe_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_x2_ck";
		dpll_abe_m2x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2x2_ck@1f0";
		abe_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/abe_clk@108";
		dpll_abe_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2_ck@1f0";
		dpll_abe_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m3x2_ck@1f4";
		dpll_core_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_byp_mux@12c";
		dpll_core_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_ck@120";
		dpll_core_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_x2_ck";
		dpll_core_h12x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h12x2_ck@13c";
		mpu_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dpll_hs_clk_div";
		dpll_mpu_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_ck@160";
		dpll_mpu_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_m2_ck@170";
		mpu_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dclk_div";
		dsp_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dsp_dpll_hs_clk_div";
		dpll_dsp_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_byp_mux@240";
		dpll_dsp_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_ck@234";
		dpll_dsp_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m2_ck@244";
		iva_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dpll_hs_clk_div";
		dpll_iva_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_byp_mux@1ac";
		dpll_iva_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_ck@1a0";
		dpll_iva_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_m2_ck@1b0";
		iva_dclk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dclk";
		dpll_gpu_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_byp_mux@2e4";
		dpll_gpu_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_ck@2d8";
		dpll_gpu_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_m2_ck@2e8";
		dpll_core_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_m2_ck@130";
		core_dpll_out_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/core_dpll_out_dclk_div";
		dpll_ddr_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_byp_mux@21c";
		dpll_ddr_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_ck@210";
		dpll_ddr_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_m2_ck@220";
		dpll_gmac_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_byp_mux@2b4";
		dpll_gmac_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_ck@2a8";
		dpll_gmac_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m2_ck@2b8";
		video2_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_dclk_div";
		video1_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_dclk_div";
		hdmi_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_dclk_div";
		per_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/per_dpll_hs_clk_div";
		usb_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_dpll_hs_clk_div";
		eve_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dpll_hs_clk_div";
		dpll_eve_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_byp_mux@290";
		dpll_eve_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_ck@284";
		dpll_eve_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_m2_ck@294";
		eve_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dclk_div";
		dpll_core_h13x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h13x2_ck@140";
		dpll_core_h14x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h14x2_ck@144";
		dpll_core_h22x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h22x2_ck@154";
		dpll_core_h23x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h23x2_ck@158";
		dpll_core_h24x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h24x2_ck@15c";
		dpll_ddr_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_x2_ck";
		dpll_ddr_h11x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_h11x2_ck@228";
		dpll_dsp_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_x2_ck";
		dpll_dsp_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m3x2_ck@248";
		dpll_gmac_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_x2_ck";
		dpll_gmac_h11x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h11x2_ck@2c0";
		dpll_gmac_h12x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h12x2_ck@2c4";
		dpll_gmac_h13x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h13x2_ck@2c8";
		dpll_gmac_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m3x2_ck@2bc";
		gmii_m_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/gmii_m_clk_div";
		hdmi_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clk2_div";
		hdmi_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_div_clk";
		l3_iclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/l3_iclk_div@100";
		l4_root_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/l4_root_clk_div";
		video1_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clk2_div";
		video1_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_div_clk";
		video2_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clk2_div";
		video2_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_div_clk";
		ipu1_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ipu1_gfclk_mux@520";
		mcasp1_ahclkr_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_ahclkr_mux@550";
		mcasp1_ahclkx_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_ahclkx_mux@550";
		mcasp1_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_aux_gfclk_mux@550";
		timer5_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer5_gfclk_mux@558";
		timer6_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer6_gfclk_mux@560";
		timer7_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer7_gfclk_mux@568";
		timer8_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer8_gfclk_mux@570";
		uart6_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/uart6_gfclk_mux@580";
		dummy_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dummy_ck";
		cm_core_aon_clockdomains = "/ocp/l4@4a000000/cm_core_aon@5000/clockdomains";
		cm_core = "/ocp/l4@4a000000/cm_core@8000";
		cm_core_clocks = "/ocp/l4@4a000000/cm_core@8000/clocks";
		dpll_pcie_ref_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_ck@200";
		dpll_pcie_ref_m2ldo_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2ldo_ck@210";
		apll_pcie_in_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_in_clk_mux@4ae06118";
		apll_pcie_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_ck@21c";
		optfclk_pciephy1_32khz = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_32khz@4a0093b0";
		optfclk_pciephy2_32khz = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_32khz@4a0093b8";
		optfclk_pciephy_div = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy_div@4a00821c";
		optfclk_pciephy1_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_clk@4a0093b0";
		optfclk_pciephy2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_clk@4a0093b8";
		optfclk_pciephy1_div_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_div_clk@4a0093b0";
		optfclk_pciephy2_div_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_div_clk@4a0093b8";
		apll_pcie_clkvcoldo = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo";
		apll_pcie_clkvcoldo_div = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo_div";
		apll_pcie_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_m2_ck";
		dpll_per_byp_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_byp_mux@14c";
		dpll_per_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_ck@140";
		dpll_per_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2_ck@150";
		func_96m_aon_dclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_aon_dclk_div";
		dpll_usb_byp_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_byp_mux@18c";
		dpll_usb_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_ck@180";
		dpll_usb_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_m2_ck@190";
		dpll_pcie_ref_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2_ck@210";
		dpll_per_x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_x2_ck";
		dpll_per_h11x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h11x2_ck@158";
		dpll_per_h12x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h12x2_ck@15c";
		dpll_per_h13x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h13x2_ck@160";
		dpll_per_h14x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h14x2_ck@164";
		dpll_per_m2x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2x2_ck@150";
		dpll_usb_clkdcoldo = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_clkdcoldo";
		func_128m_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_128m_clk";
		func_12m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_12m_fclk";
		func_24m_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_24m_clk";
		func_48m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_48m_fclk";
		func_96m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_fclk";
		l3init_60m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/l3init_60m_fclk@104";
		clkout2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/clkout2_clk@6b0";
		l3init_960m_gfclk = "/ocp/l4@4a000000/cm_core@8000/clocks/l3init_960m_gfclk@6c0";
		dss_32khz_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_32khz_clk@1120";
		dss_48mhz_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_48mhz_clk@1120";
		dss_dss_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_dss_clk@1120";
		dss_hdmi_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_hdmi_clk@1120";
		dss_video1_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_video1_clk@1120";
		dss_video2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_video2_clk@1120";
		gpio2_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio2_dbclk@1760";
		gpio3_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio3_dbclk@1768";
		gpio4_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio4_dbclk@1770";
		gpio5_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio5_dbclk@1778";
		gpio6_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio6_dbclk@1780";
		gpio7_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio7_dbclk@1810";
		gpio8_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio8_dbclk@1818";
		mmc1_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_clk32k@1328";
		mmc2_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_clk32k@1330";
		mmc3_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_clk32k@1820";
		mmc4_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_clk32k@1828";
		sata_ref_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/sata_ref_clk@1388";
		usb_otg_ss1_refclk960m = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_otg_ss1_refclk960m@13f0";
		usb_otg_ss2_refclk960m = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_otg_ss2_refclk960m@1340";
		usb_phy1_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy1_always_on_clk32k@640";
		usb_phy2_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy2_always_on_clk32k@688";
		usb_phy3_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy3_always_on_clk32k@698";
		atl_dpll_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/atl_dpll_clk_mux@c00";
		atl_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/atl_gfclk_mux@c00";
		rmii_50mhz_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/rmii_50mhz_clk_mux@13d0";
		gmac_rft_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gmac_rft_clk_mux@13d0";
		gpu_core_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gpu_core_gclk_mux@1220";
		gpu_hyd_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gpu_hyd_gclk_mux@1220";
		l3instr_ts_gclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/l3instr_ts_gclk_div@e50";
		mcasp2_ahclkr_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_ahclkr_mux@1860";
		mcasp2_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_ahclkx_mux@1860";
		mcasp2_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_aux_gfclk_mux@1860";
		mcasp3_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp3_ahclkx_mux@1868";
		mcasp3_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp3_aux_gfclk_mux@1868";
		mcasp4_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp4_ahclkx_mux@1898";
		mcasp4_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp4_aux_gfclk_mux@1898";
		mcasp5_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp5_ahclkx_mux@1878";
		mcasp5_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp5_aux_gfclk_mux@1878";
		mcasp6_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp6_ahclkx_mux@1904";
		mcasp6_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp6_aux_gfclk_mux@1904";
		mcasp7_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp7_ahclkx_mux@1908";
		mcasp7_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp7_aux_gfclk_mux@1908";
		mcasp8_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp8_ahclkx_mux@1890";
		mcasp8_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp8_aux_gfclk_mux@1890";
		mmc1_fclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_fclk_mux@1328";
		mmc1_fclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_fclk_div@1328";
		mmc2_fclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_fclk_mux@1330";
		mmc2_fclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_fclk_div@1330";
		mmc3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_gfclk_mux@1820";
		mmc3_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_gfclk_div@1820";
		mmc4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_gfclk_mux@1828";
		mmc4_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_gfclk_div@1828";
		qspi_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/qspi_gfclk_mux@1838";
		qspi_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/qspi_gfclk_div@1838";
		timer10_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer10_gfclk_mux@1728";
		timer11_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer11_gfclk_mux@1730";
		timer13_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer13_gfclk_mux@17c8";
		timer14_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer14_gfclk_mux@17d0";
		timer15_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer15_gfclk_mux@17d8";
		timer16_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer16_gfclk_mux@1830";
		timer2_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer2_gfclk_mux@1738";
		timer3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer3_gfclk_mux@1740";
		timer4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer4_gfclk_mux@1748";
		timer9_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer9_gfclk_mux@1750";
		uart1_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart1_gfclk_mux@1840";
		uart2_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart2_gfclk_mux@1848";
		uart3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart3_gfclk_mux@1850";
		uart4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart4_gfclk_mux@1858";
		uart5_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart5_gfclk_mux@1870";
		uart7_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart7_gfclk_mux@18d0";
		uart8_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart8_gfclk_mux@18e0";
		uart9_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart9_gfclk_mux@18e8";
		vip1_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip1_gclk_mux@1020";
		vip2_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip2_gclk_mux@1028";
		vip3_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip3_gclk_mux@1030";
		cm_core_clockdomains = "/ocp/l4@4a000000/cm_core@8000/clockdomains";
		coreaon_clkdm = "/ocp/l4@4a000000/cm_core@8000/clockdomains/coreaon_clkdm";
		l4_wkup = "/ocp/l4@4ae00000";
		counter32k = "/ocp/l4@4ae00000/counter@4000";
		prm = "/ocp/l4@4ae00000/prm@6000";
		prm_clocks = "/ocp/l4@4ae00000/prm@6000/clocks";
		sys_clkin1 = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clkin1@110";
		abe_dpll_sys_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_sys_clk_mux@118";
		abe_dpll_bypass_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_bypass_clk_mux@114";
		abe_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_clk_mux@10c";
		abe_24m_fclk = "/ocp/l4@4ae00000/prm@6000/clocks/abe_24m_fclk@11c";
		aess_fclk = "/ocp/l4@4ae00000/prm@6000/clocks/aess_fclk@178";
		abe_giclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_giclk_div@174";
		abe_lp_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_lp_clk_div@1d8";
		abe_sys_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_sys_clk_div@120";
		adc_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/adc_gfclk_mux@1dc";
		sys_clk1_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clk1_dclk_div@1c8";
		sys_clk2_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clk2_dclk_div@1cc";
		per_abe_x1_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_dclk_div@1bc";
		dsp_gclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/dsp_gclk_div@18c";
		gpu_dclk = "/ocp/l4@4ae00000/prm@6000/clocks/gpu_dclk@1a0";
		emif_phy_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/emif_phy_dclk_div@190";
		gmac_250m_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/gmac_250m_dclk_div@19c";
		gmac_main_clk = "/ocp/l4@4ae00000/prm@6000/clocks/gmac_main_clk";
		l3init_480m_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/l3init_480m_dclk_div@1ac";
		usb_otg_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/usb_otg_dclk_div@184";
		sata_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sata_dclk_div@1c0";
		pcie2_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/pcie2_dclk_div@1b8";
		pcie_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/pcie_dclk_div@1b4";
		emu_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/emu_dclk_div@194";
		secure_32k_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/secure_32k_dclk_div@1c4";
		clkoutmux0_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux0_clk_mux@158";
		clkoutmux1_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux1_clk_mux@15c";
		clkoutmux2_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux2_clk_mux@160";
		custefuse_sys_gfclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/custefuse_sys_gfclk_div";
		eve_clk = "/ocp/l4@4ae00000/prm@6000/clocks/eve_clk@180";
		hdmi_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/hdmi_dpll_clk_mux@164";
		mlb_clk = "/ocp/l4@4ae00000/prm@6000/clocks/mlb_clk@134";
		mlbp_clk = "/ocp/l4@4ae00000/prm@6000/clocks/mlbp_clk@130";
		per_abe_x1_gfclk2_div = "/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_gfclk2_div@138";
		timer_sys_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/timer_sys_clk_div@144";
		video1_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/video1_dpll_clk_mux@168";
		video2_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/video2_dpll_clk_mux@16c";
		wkupaon_iclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/wkupaon_iclk_mux@108";
		gpio1_dbclk = "/ocp/l4@4ae00000/prm@6000/clocks/gpio1_dbclk@1838";
		dcan1_sys_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/dcan1_sys_clk_mux@1888";
		timer1_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/timer1_gfclk_mux@1840";
		uart10_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/uart10_gfclk_mux@1880";
		prm_clockdomains = "/ocp/l4@4ae00000/prm@6000/clockdomains";
		scm_wkup = "/ocp/l4@4ae00000/scm_conf@c000";
		pcie1_rc = "/ocp/axi@0/pcie@51000000";
		pcie1_intc = "/ocp/axi@0/pcie@51000000/interrupt-controller";
		pcie1_ep = "/ocp/axi@0/pcie_ep@51000000";
		pcie2_rc = "/ocp/axi@1/pcie@51800000";
		pcie2_intc = "/ocp/axi@1/pcie@51800000/interrupt-controller";
		ocmcram1 = "/ocp/ocmcram@40300000";
		ocmcram2 = "/ocp/ocmcram@40400000";
		ocmcram3 = "/ocp/ocmcram@40500000";
		bandgap = "/ocp/bandgap@4a0021e0";
		dsp1_system = "/ocp/dsp_system@40d00000";
		dra7_iodelay_core = "/ocp/padconf@4844a000";
		mmc1_iodelay_ddr_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr_rev11_conf";
		mmc1_iodelay_ddr_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr50_rev20_conf";
		mmc1_iodelay_sdr104_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev11_conf";
		mmc1_iodelay_sdr104_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev20_conf";
		mmc2_iodelay_hs200_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev11_conf";
		mmc2_iodelay_hs200_rev20_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev20_conf";
		mmc2_iodelay_ddr_3_3v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_3_3v_rev11_conf";
		mmc2_iodelay_ddr_1_8v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_1_8v_rev11_conf";
		mmc3_iodelay_manual1_rev11_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
		mmc3_iodelay_manual1_rev20_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
		mmc4_iodelay_ds_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev11_conf";
		mmc4_iodelay_ds_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev20_conf";
		mmc4_iodelay_sdr12_hs_sdr25_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev11_conf";
		mmc4_iodelay_sdr12_hs_sdr25_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev20_conf";
		sdma = "/ocp/dma-controller@4a056000";
		edma = "/ocp/edma@43300000";
		edma_tptc0 = "/ocp/tptc@43400000";
		edma_tptc1 = "/ocp/tptc@43500000";
		gpio1 = "/ocp/gpio@4ae10000";
		gpio2 = "/ocp/gpio@48055000";
		gpio3 = "/ocp/gpio@48057000";
		gpio4 = "/ocp/gpio@48059000";
		gpio5 = "/ocp/gpio@4805b000";
		gpio6 = "/ocp/gpio@4805d000";
		gpio7 = "/ocp/gpio@48051000";
		gpio8 = "/ocp/gpio@48053000";
		uart1 = "/ocp/serial@4806a000";
		uart2 = "/ocp/serial@4806c000";
		uart3 = "/ocp/serial@48020000";
		uart4 = "/ocp/serial@4806e000";
		uart5 = "/ocp/serial@48066000";
		uart6 = "/ocp/serial@48068000";
		uart7 = "/ocp/serial@48420000";
		uart8 = "/ocp/serial@48422000";
		uart9 = "/ocp/serial@48424000";
		uart10 = "/ocp/serial@4ae2b000";
		mailbox1 = "/ocp/mailbox@4a0f4000";
		mailbox2 = "/ocp/mailbox@4883a000";
		mailbox3 = "/ocp/mailbox@4883c000";
		mailbox4 = "/ocp/mailbox@4883e000";
		mailbox5 = "/ocp/mailbox@48840000";
		mbox_ipu1_ipc3x = "/ocp/mailbox@48840000/mbox_ipu1_ipc3x";
		mbox_dsp1_ipc3x = "/ocp/mailbox@48840000/mbox_dsp1_ipc3x";
		mailbox6 = "/ocp/mailbox@48842000";
		mbox_ipu2_ipc3x = "/ocp/mailbox@48842000/mbox_ipu2_ipc3x";
		mbox_dsp2_ipc3x = "/ocp/mailbox@48842000/mbox_dsp2_ipc3x";
		mailbox7 = "/ocp/mailbox@48844000";
		mailbox8 = "/ocp/mailbox@48846000";
		mailbox9 = "/ocp/mailbox@4885e000";
		mailbox10 = "/ocp/mailbox@48860000";
		mailbox11 = "/ocp/mailbox@48862000";
		mailbox12 = "/ocp/mailbox@48864000";
		mailbox13 = "/ocp/mailbox@48802000";
		timer1 = "/ocp/timer@4ae18000";
		timer2 = "/ocp/timer@48032000";
		timer3 = "/ocp/timer@48034000";
		timer4 = "/ocp/timer@48036000";
		timer5 = "/ocp/timer@48820000";
		timer6 = "/ocp/timer@48822000";
		timer7 = "/ocp/timer@48824000";
		timer8 = "/ocp/timer@48826000";
		timer9 = "/ocp/timer@4803e000";
		timer10 = "/ocp/timer@48086000";
		timer11 = "/ocp/timer@48088000";
		timer12 = "/ocp/timer@4ae20000";
		timer13 = "/ocp/timer@48828000";
		timer14 = "/ocp/timer@4882a000";
		timer15 = "/ocp/timer@4882c000";
		timer16 = "/ocp/timer@4882e000";
		wdt2 = "/ocp/wdt@4ae14000";
		hwspinlock = "/ocp/spinlock@4a0f6000";
		ipu1 = "/ocp/ipu@58820000";
		ipu2 = "/ocp/ipu@55020000";
		dsp1 = "/ocp/dsp@40800000";
		i2c1 = "/ocp/i2c@48070000";
		tps659038 = "/ocp/i2c@48070000/tps659038@58";
		smps12_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps12";
		smps3_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps3";
		smps45_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps45";
		smps6_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps6";
		smps8_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps8";
		ldo1_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo1";
		ldo2_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo2";
		ldo3_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo3";
		ldo4_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo4";
		ldo9_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo9";
		ldoln_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldoln";
		ldousb_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldousb";
		regen1 = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/regen1";
		tps659038_rtc = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
		tps659038_pwr_button = "/ocp/i2c@48070000/tps659038@58/tps659038_pwr_button";
		tps659038_gpio = "/ocp/i2c@48070000/tps659038@58/tps659038_gpio";
		extcon_usb2 = "/ocp/i2c@48070000/tps659038@58/tps659038_usb";
		tmp102 = "/ocp/i2c@48070000/tmp102@48";
		tlv320aic3104 = "/ocp/i2c@48070000/tlv320aic3104@18";
		eeprom = "/ocp/i2c@48070000/eeprom@50";
		i2c2 = "/ocp/i2c@48072000";
		i2c3 = "/ocp/i2c@48060000";
		mcp_rtc = "/ocp/i2c@48060000/rtc@6f";
		i2c4 = "/ocp/i2c@4807a000";
		i2c5 = "/ocp/i2c@4807c000";
		mmc1 = "/ocp/mmc@4809c000";
		mmc2 = "/ocp/mmc@480b4000";
		mmc3 = "/ocp/mmc@480ad000";
		mmc4 = "/ocp/mmc@480d1000";
		mmu0_dsp1 = "/ocp/mmu@40d01000";
		mmu1_dsp1 = "/ocp/mmu@40d02000";
		mmu_ipu1 = "/ocp/mmu@58882000";
		mmu_ipu2 = "/ocp/mmu@55082000";
		pruss_soc_bus1 = "/ocp/pruss_soc_bus@4b226004";
		pruss1 = "/ocp/pruss_soc_bus@4b226004/pruss@0";
		pruss1_mem = "/ocp/pruss_soc_bus@4b226004/pruss@0/memories@0";
		pruss1_cfg = "/ocp/pruss_soc_bus@4b226004/pruss@0/cfg@26000";
		pruss1_mii_rt = "/ocp/pruss_soc_bus@4b226004/pruss@0/mii_rt@32000";
		pruss1_intc = "/ocp/pruss_soc_bus@4b226004/pruss@0/intc@20000";
		pru1_0 = "/ocp/pruss_soc_bus@4b226004/pruss@0/pru@34000";
		pru1_1 = "/ocp/pruss_soc_bus@4b226004/pruss@0/pru@38000";
		pruss1_mdio = "/ocp/pruss_soc_bus@4b226004/pruss@0/mdio@32400";
		pruss_soc_bus2 = "/ocp/pruss_soc_bus@4b2a6004";
		pruss2 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0";
		pruss2_mem = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/memories@0";
		pruss2_cfg = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/cfg@26000";
		pruss2_iep = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/iep@2e000";
		pruss2_mii_rt = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/mii_rt@32000";
		pruss2_intc = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/intc@20000";
		pru2_0 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/pru@34000";
		pru2_1 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/pru@38000";
		pruss2_mdio = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/mdio@32400";
		abb_mpu = "/ocp/regulator-abb-mpu";
		abb_ivahd = "/ocp/regulator-abb-ivahd";
		abb_dspeve = "/ocp/regulator-abb-dspeve";
		abb_gpu = "/ocp/regulator-abb-gpu";
		mcspi1 = "/ocp/spi@48098000";
		mcspi2 = "/ocp/spi@4809a000";
		mcspi3 = "/ocp/spi@480b8000";
		mcspi4 = "/ocp/spi@480ba000";
		qspi = "/ocp/qspi@4b300000";
		sata_phy = "/ocp/ocp2scp@4a090000/phy@4A096000";
		pcie1_phy = "/ocp/ocp2scp@4a090000/pciephy@4a094000";
		pcie2_phy = "/ocp/ocp2scp@4a090000/pciephy@4a095000";
		sata = "/ocp/sata@4a141100";
		rtc = "/ocp/rtc@48838000";
		usb2_phy1 = "/ocp/ocp2scp@4a080000/phy@4a084000";
		usb2_phy2 = "/ocp/ocp2scp@4a080000/phy@4a085000";
		usb3_phy1 = "/ocp/ocp2scp@4a080000/phy@4a084400";
		omap_dwc3_1 = "/ocp/omap_dwc3_1@48880000";
		usb1 = "/ocp/omap_dwc3_1@48880000/usb@48890000";
		omap_dwc3_2 = "/ocp/omap_dwc3_2@488c0000";
		usb2 = "/ocp/omap_dwc3_2@488c0000/usb@488d0000";
		omap_dwc3_3 = "/ocp/omap_dwc3_3@48900000";
		usb3 = "/ocp/omap_dwc3_3@48900000/usb@48910000";
		elm = "/ocp/elm@48078000";
		gpmc = "/ocp/gpmc@50000000";
		atl = "/ocp/atl@4843c000";
		mcasp1 = "/ocp/mcasp@48460000";
		mcasp2 = "/ocp/mcasp@48464000";
		mcasp3 = "/ocp/mcasp@48468000";
		mcasp4 = "/ocp/mcasp@4846c000";
		mcasp5 = "/ocp/mcasp@48470000";
		mcasp6 = "/ocp/mcasp@48474000";
		mcasp7 = "/ocp/mcasp@48478000";
		mcasp8 = "/ocp/mcasp@4847c000";
		crossbar_mpu = "/ocp/crossbar@4a002a48";
		mac = "/ocp/ethernet@48484000";
		davinci_mdio = "/ocp/ethernet@48484000/mdio@48485000";
		phy0 = "/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@1";
		phy1 = "/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@2";
		cpsw_emac0 = "/ocp/ethernet@48484000/slave@48480200";
		cpsw_emac1 = "/ocp/ethernet@48484000/slave@48480300";
		phy_sel = "/ocp/ethernet@48484000/cpsw-phy-sel@4a002554";
		dcan1 = "/ocp/can@4ae3c000";
		dcan2 = "/ocp/can@48480000";
		gpu = "/ocp/gpu@56000000";
		bb2d = "/ocp/bb2d@59000000";
		dss = "/ocp/dss@58000000";
		hdmi = "/ocp/dss@58000000/encoder@58060000";
		hdmi_out = "/ocp/dss@58000000/encoder@58060000/port/endpoint";
		epwmss0 = "/ocp/epwmss@4843e000";
		ehrpwm0 = "/ocp/epwmss@4843e000/pwm@4843e200";
		ecap0 = "/ocp/epwmss@4843e000/ecap@4843e100";
		epwmss1 = "/ocp/epwmss@48440000";
		ehrpwm1 = "/ocp/epwmss@48440000/pwm@48440200";
		ecap1 = "/ocp/epwmss@48440000/ecap@48440100";
		epwmss2 = "/ocp/epwmss@48442000";
		ehrpwm2 = "/ocp/epwmss@48442000/pwm@48442200";
		ecap2 = "/ocp/epwmss@48442000/ecap@48442100";
		aes1 = "/ocp/aes@4b500000";
		aes2 = "/ocp/aes@4b700000";
		des = "/ocp/des@480a5000";
		sham = "/ocp/sham@53100000";
		rng = "/ocp/rng@48090000";
		opp_supply_mpu = "/ocp/opp-supply@4a003b20";
		vip1 = "/ocp/vip@0x48970000";
		vin1a = "/ocp/vip@0x48970000/port@0";
		vin2a = "/ocp/vip@0x48970000/port@1";
		vin1b = "/ocp/vip@0x48970000/port@2";
		vin2b = "/ocp/vip@0x48970000/port@3";
		dsp2_system = "/ocp/dsp_system@41500000";
		omap_dwc3_4 = "/ocp/omap_dwc3_4@48940000";
		usb4 = "/ocp/omap_dwc3_4@48940000/usb@48950000";
		mmu0_dsp2 = "/ocp/mmu@41501000";
		mmu1_dsp2 = "/ocp/mmu@41502000";
		dsp2 = "/ocp/dsp@41000000";
		vip2 = "/ocp/vip@0x48990000";
		vin3a = "/ocp/vip@0x48990000/port@0";
		vin4a = "/ocp/vip@0x48990000/port@1";
		vin3b = "/ocp/vip@0x48990000/port@2";
		vin4b = "/ocp/vip@0x48990000/port@3";
		vip3 = "/ocp/vip@0x489b0000";
		vin5a = "/ocp/vip@0x489b0000/port@0";
		vin6a = "/ocp/vip@0x489b0000/port@1";
		thermal_zones = "/thermal-zones";
		cpu_thermal = "/thermal-zones/cpu_thermal";
		cpu_trips = "/thermal-zones/cpu_thermal/trips";
		cpu_alert0 = "/thermal-zones/cpu_thermal/trips/cpu_alert";
		cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
		cpu_alert1 = "/thermal-zones/cpu_thermal/trips/cpu_alert1";
		cpu_cooling_maps = "/thermal-zones/cpu_thermal/cooling-maps";
		gpu_thermal = "/thermal-zones/gpu_thermal";
		gpu_crit = "/thermal-zones/gpu_thermal/trips/gpu_crit";
		core_thermal = "/thermal-zones/core_thermal";
		core_crit = "/thermal-zones/core_thermal/trips/core_crit";
		dspeve_thermal = "/thermal-zones/dspeve_thermal";
		dspeve_crit = "/thermal-zones/dspeve_thermal/trips/dspeve_crit";
		iva_thermal = "/thermal-zones/iva_thermal";
		iva_crit = "/thermal-zones/iva_thermal/trips/iva_crit";
		board_thermal = "/thermal-zones/board_thermal";
		board_trips = "/thermal-zones/board_thermal/trips";
		board_alert0 = "/thermal-zones/board_thermal/trips/board_alert";
		board_crit = "/thermal-zones/board_thermal/trips/board_crit";
		board_cooling_maps = "/thermal-zones/board_thermal/cooling-maps";
		ipu2_memory_region = "/reserved-memory/ipu2-memory@95800000";
		dsp1_memory_region = "/reserved-memory/dsp1-memory@99000000";
		ipu1_memory_region = "/reserved-memory/ipu1-memory@9d000000";
		dsp2_memory_region = "/reserved-memory/dsp2-memory@9f000000";
		cmem_block_mem_0 = "/reserved-memory/cmem_block_mem@a0000000";
		cmem_block_mem_1_ocmc3 = "/reserved-memory/cmem_block_mem@40500000";
		main_12v0 = "/fixedregulator-main_12v0";
		evm_5v0 = "/fixedregulator-evm_5v0";
		vdd_3v3 = "/fixedregulator-vdd_3v3";
		aic_dvdd = "/fixedregulator-aic_dvdd";
		vtt_fixed = "/fixedregulator-vtt";
		gpio_fan = "/gpio_fan";
		hdmi0 = "/connector";
		hdmi_connector_in = "/connector/port/endpoint";
		tpd12s015 = "/encoder";
		tpd12s015_in = "/encoder/ports/port@0/endpoint";
		tpd12s015_out = "/encoder/ports/port@1/endpoint";
		sound0 = "/sound0";
		sound0_master = "/sound0/simple-audio-card,codec";
		cmem_block_0 = "/cmem/cmem_block@0";
		cmem_block_1 = "/cmem/cmem_block@1";
	};
};

Anton,

Could you try removing:

mmc-ddr-1_8v, cd-gpios & vqmmc-supply properties from mmc1 node?

- Keerthy

Hi, Keerthy J. Sorry for reply delay, I am had not getting email notification on your answer =(

My custom board has only mmc1 (sd-card). The system successfully boot from network, but cannot boot from sd-card. I have conducted some experiments:

1. sd-card is successfully mounting on my host and I can read and write from/in both partitions.

2. I am successfully getting lists of partitions content from u-boot.

=> fatls mmc 0:1
    99308   MLO
   588200   u-boot.img
            .Trash-0/
            System Volume Information/

2 file(s), 2 dir(s)

=> ext4ls mmc 0:2
<DIR>       4096 .
<DIR>       4096 ..
<DIR>       4096 bin
<DIR>      12288 boot
<DIR>       4096 dev
<DIR>       4096 etc
<DIR>       4096 home
<DIR>       4096 include
<DIR>       4096 lib
<DIR>       4096 media
<DIR>       4096 mnt
<DIR>       4096 opt
<DIR>       4096 proc
<DIR>       4096 run
<DIR>       4096 sbin
<DIR>       4096 srv
<DIR>       4096 sys
<DIR>       4096 tmp
<DIR>       4096 usr
<DIR>       4096 var

3. I set cd-inverted attribute in u-boot and boot stopped at beginning therefore i removed it.

4. I setted up mmc with "broken-cd" and "non-removable" but boot is stucked on "Waiting for root device PARTUUID=a464469c-02...".

5. I changed mmcrootfstype from "ext4 rootwait" to "ext4" only and try to boot - unsuccessful.

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.79-gbde58ab01e (khrenkov@khrenkov-sitar) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #1 SMP PREEMPT Wed Aug 18 16:43:08 +07 2021
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: TI AM5728 EVM
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000fe400000
[    0.000000] OMAP4: Map 0x00000000ffd00000 to fe600000 for dram barrier
[    0.000000] On node 0 totalpages: 474368
[    0.000000] free_area_init_node: node 0, pgdat c1053d80, node_mem_map eeda2000
[    0.000000]   DMA zone: 1728 pages used for memmap
[    0.000000]   DMA zone: 0 pages reserved
[    0.000000]   DMA zone: 147456 pages, LIFO batch:31
[    0.000000]   HighMem zone: 326912 pages, LIFO batch:31
[    0.000000] DRA752 ES2.0
[    0.000000] percpu: Embedded 15 pages/cpu @eed29000 s31372 r8192 d21876 u61440
[    0.000000] pcpu-alloc: s31372 r8192 d21876 u61440 alloc=15*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 472640
[    0.000000] Kernel command line: console=ttyO2,115200n8 root=PARTUUID=a464469c-02 rw rootfstype=ext4
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1675572K/1897472K available (8192K kernel code, 347K rwdata, 2564K rodata, 2048K init, 282K bss, 33484K reserved, 188416K cma-reserved, 1283072K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0a00000   (10208 kB)
[    0.000000]       .init : 0xc0e00000 - 0xc1000000   (2048 kB)
[    0.000000]       .data : 0xc1000000 - 0xc1056e98   ( 348 kB)
[    0.000000]        .bss : 0xc1058000 - 0xc109ebe0   ( 283 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Tasks RCU enabled.
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000005] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000017] Switching to timer-based delay loop, resolution 162ns
[    0.000353] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000361] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000878] Console: colour dummy device 80x30
[    0.000895] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
[    0.000902] This ensures that you still see kernel messages. Please
[    0.000909] update your kernel commandline.
[    0.000931] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.000946] pid_max: default: 32768 minimum: 301
[    0.001064] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001078] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001613] CPU: Testing write buffer coherency: ok
[    0.001651] CPU0: Spectre v2: using ICIALLU workaround
[    0.001849] /cpus/cpu@0 missing clock-frequency property
[    0.001867] /cpus/cpu@1 missing clock-frequency property
[    0.001879] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.039848] Setting up static identity map for 0x80200000 - 0x80200060
[    0.059856] Hierarchical SRCU implementation.
[    0.080050] EFI services will not be available.
[    0.099921] smp: Bringing up secondary CPUs ...
[    0.170285] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.170290] CPU1: Spectre v2: using ICIALLU workaround
[    0.170393] smp: Brought up 1 node, 2 CPUs
[    0.170404] SMP: Total of 2 processors activated (24.59 BogoMIPS).
[    0.170412] CPU: All CPU(s) started in HYP mode.
[    0.170420] CPU: Virtualization extensions available.
[    0.170952] devtmpfs: initialized
[    0.191586] random: get_random_u32 called from bucket_table_alloc+0x108/0x230 with crng_init=0
[    0.191824] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.192016] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.192033] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.195803] pinctrl core: initialized pinctrl subsystem
[    0.196249] DMI not present or invalid.
[    0.196503] NET: Registered protocol family 16
[    0.197536] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.198484] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.410825] cpuidle: using governor ladder
[    0.410858] cpuidle: using governor menu
[    0.419337] gpio gpiochip0: (gpio): added GPIO chardev (254:0)
[    0.419406] gpiochip_setup_dev: registered GPIOs 0 to 31 on device: gpiochip0 (gpio)
[    0.419465] OMAP GPIO hardware version 0.1
[    0.420102] gpio gpiochip1: (gpio): added GPIO chardev (254:1)
[    0.420171] gpiochip_setup_dev: registered GPIOs 32 to 63 on device: gpiochip1 (gpio)
[    0.420873] gpio gpiochip2: (gpio): added GPIO chardev (254:2)
[    0.420944] gpiochip_setup_dev: registered GPIOs 64 to 95 on device: gpiochip2 (gpio)
[    0.421608] gpio gpiochip3: (gpio): added GPIO chardev (254:3)
[    0.421673] gpiochip_setup_dev: registered GPIOs 96 to 127 on device: gpiochip3 (gpio)
[    0.422335] gpio gpiochip4: (gpio): added GPIO chardev (254:4)
[    0.422399] gpiochip_setup_dev: registered GPIOs 128 to 159 on device: gpiochip4 (gpio)
[    0.423065] gpio gpiochip5: (gpio): added GPIO chardev (254:5)
[    0.423129] gpiochip_setup_dev: registered GPIOs 160 to 191 on device: gpiochip5 (gpio)
[    0.423783] gpio gpiochip6: (gpio): added GPIO chardev (254:6)
[    0.423855] gpiochip_setup_dev: registered GPIOs 192 to 223 on device: gpiochip6 (gpio)
[    0.424516] gpio gpiochip7: (gpio): added GPIO chardev (254:7)
[    0.424584] gpiochip_setup_dev: registered GPIOs 224 to 255 on device: gpiochip7 (gpio)
[    0.446697] No ATAGs?
[    0.446773] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.446787] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.447173] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.447184] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.447715] OMAP DMA hardware revision 0.0
[    0.457407] edma 43300000.edma: memcpy is disabled
[    0.460597] edma 43300000.edma: TI EDMA DMA engine driver
[    0.467185] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.467558] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-mmcwl[0]' - status (0)
[    0.467818] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-com_3v6[0]'
[    0.468231] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-main_12v0[0]'
[    0.468460] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-evm_5v0[0]'
[    0.468511] evm_5v0: supplied by main_12v0
[    0.468764] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-vdd_3v3[0]'
[    0.468937] com_3v6: supplied by evm_5v0
[    0.469081] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-aic_dvdd[0]'
[    0.469432] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-vtt[0]' - status (0)
[    0.471982] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.472175] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.472415] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.472647] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.473007] omap-iommu 41501000.mmu: 41501000.mmu registered
[    0.473216] omap-iommu 41502000.mmu: 41502000.mmu registered
[    0.473471] iommu: Adding device 58820000.ipu to group 1
[    0.473560] iommu: Adding device 55020000.ipu to group 2
[    0.473719] iommu: Adding device 40800000.dsp to group 0
[    0.473983] iommu: Adding device 41000000.dsp to group 3
[    0.476297] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    0.476799] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
[    0.477281] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
[    0.477450] media: Linux media interface: v0.10
[    0.477486] Linux video capture interface: v2.00
[    0.477561] pps_core: LinuxPPS API ver. 1 registered
[    0.477569] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.477589] PTP clock support registered
[    0.477616] EDAC MC: Ver: 3.0.0
[    0.477857] dmi: Firmware registration failed.
[    0.478246] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.478519] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.478837] Advanced Linux Sound Architecture Driver Initialized.
[    0.479529] clocksource: Switched to clocksource arch_sys_counter
[    0.487200] NET: Registered protocol family 2
[    0.487715] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.487779] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.487905] TCP: Hash tables configured (established 8192 bind 8192)
[    0.487973] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.488005] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.488129] NET: Registered protocol family 1
[    0.488446] RPC: Registered named UNIX socket transport module.
[    0.488456] RPC: Registered udp transport module.
[    0.488464] RPC: Registered tcp transport module.
[    0.488471] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.488481] PCI: CLS 0 bytes, default 64
[    0.489352] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    0.489576] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.490573] workingset: timestamp_bits=14 max_order=19 bucket_order=5
[    0.494604] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.495104] NFS: Registering the id_resolver key type
[    0.495133] Key type id_resolver registered
[    0.495142] Key type id_legacy registered
[    0.495179] ntfs: driver 2.1.32 [Flags: R/O].
[    0.496483] bounce: pool size: 64 pages
[    0.496524] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.496535] io scheduler noop registered
[    0.496544] io scheduler deadline registered
[    0.496637] io scheduler cfq registered (default)
[    0.496647] io scheduler mq-deadline registered
[    0.496655] io scheduler kyber registered
[    0.501027] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    0.504247] dra7-pcie 51000000.pcie: Linked as a consumer to phy-4a094000.pciephy.1
[    0.504406] dra7-pcie 51000000.pcie: GPIO lookup for consumer (null)
[    0.504417] dra7-pcie 51000000.pcie: using device tree for GPIO lookup
[    0.504453] of_get_named_gpiod_flags: parsed 'gpios' property of node '/ocp/axi@0/pcie@51000000[0]' - status (0)
[    0.504622] OF: PCI: host bridge /ocp/axi@0/pcie@51000000 ranges:
[    0.504657] OF: PCI:    IO 0x20003000..0x20012fff -> 0x00000000
[    0.504679] OF: PCI:   MEM 0x20013000..0x2fffffff -> 0x20013000
[    1.504950] dra7-pcie 51000000.pcie: phy link never came up
[    1.505082] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
[    1.505095] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.505106] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.505117] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[    1.505151] pci 0000:00:00.0: [104c:8888] type 01 class 0x060400
[    1.505185] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit]
[    1.505248] pci 0000:00:00.0: supports D1
[    1.505258] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    1.505442] PCI: bus0: Fast back to back transfers disabled
[    1.505530] PCI: bus1: Fast back to back transfers enabled
[    1.505568] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff 64bit]
[    1.505586] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    1.505892] pcieport 0000:00:00.0: Signaling PME with IRQ 167
[    1.506017] pcieport 0000:00:00.0: AER enabled with IRQ 167
[    1.506777] pwm-backlight backlight: GPIO lookup for consumer enable
[    1.506788] pwm-backlight backlight: using device tree for GPIO lookup
[    1.506801] of_get_named_gpiod_flags: can't parse 'enable-gpios' property of node '/backlight[0]'
[    1.506811] of_get_named_gpiod_flags: can't parse 'enable-gpio' property of node '/backlight[0]'
[    1.506821] pwm-backlight backlight: using lookup tables for GPIO lookup
[    1.506831] pwm-backlight backlight: lookup for GPIO enable failed
[    1.506853] pwm-backlight backlight: backlight supply power not found, using dummy regulator
[    1.551653] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    1.554282] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 45, base_baud = 3000000) is a 8250
[    2.860529] console [ttyS2] enabled
[    2.864842] 48422000.serial: ttyS7 at MMIO 0x48422000 (irq = 46, base_baud = 3000000) is a 8250
[    2.875459] omap_rng 48090000.rng: Random Number Generator ver. 20
[    2.883893] tpd12s015 encoder: failed to find video source
[    2.890072] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    2.898773] connector-hdmi connector: failed to find video source
[    2.905008] panel-dpi display: GPIO lookup for consumer enable
[    2.910888] panel-dpi display: using device tree for GPIO lookup
[    2.916947] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    2.926409] panel-dpi display: GPIO lookup for consumer reset
[    2.932197] panel-dpi display: using device tree for GPIO lookup
[    2.938232] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    2.946902] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    2.955479] panel-dpi display: using lookup tables for GPIO lookup
[    2.961702] panel-dpi display: lookup for GPIO reset failed
[    2.967315] panel-dpi display: display supply vcc not found, using dummy regulator
[    2.975038] panel-dpi display: failed to find video source
[    2.990680] brd: module loaded
[    2.999155] loop: module loaded
[    3.005227] mdio_bus fixed-0: GPIO lookup for consumer reset
[    3.010943] mdio_bus fixed-0: using lookup tables for GPIO lookup
[    3.017067] mdio_bus fixed-0: lookup for GPIO reset failed
[    3.022633] libphy: Fixed MDIO Bus: probed
[    3.029309] mdio_bus 48485000.mdio: GPIO lookup for consumer reset
[    3.035543] mdio_bus 48485000.mdio: using device tree for GPIO lookup
[    3.042041] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    3.053153] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    3.064177] mdio_bus 48485000.mdio: using lookup tables for GPIO lookup
[    3.070843] mdio_bus 48485000.mdio: lookup for GPIO reset failed
[    3.129586] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    3.137278] libphy: 48485000.mdio: probed
[    3.146244] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver Micrel KSZ9031 Gigabit PHY
[    3.155988] davinci_mdio 48485000.mdio: phy[2]: device 48485000.mdio:02, driver Micrel KSZ9031 Gigabit PHY
[    3.166267] cpsw 48484000.ethernet: Detected MACID = b0:7e:11:03:13:7b
[    3.172900] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[    3.179283] cpsw 48484000.ethernet: ALE Table size 1024
[    3.184580] cpsw 48484000.ethernet: device node lookup for pps timer failed
[    3.191628] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[    3.199490] cpsw 48484000.ethernet: cpsw: Detected MACID = b0:7e:11:03:13:7b
[    3.207692] i2c /dev entries driver
[    3.212105] IR NEC protocol handler initialized
[    3.216657] IR RC5(x/sz) protocol handler initialized
[    3.221753] IR RC6 protocol handler initialized
[    3.226304] IR JVC protocol handler initialized
[    3.230871] IR Sony protocol handler initialized
[    3.235509] IR SANYO protocol handler initialized
[    3.240428] IR Sharp protocol handler initialized
[    3.245154] IR MCE Keyboard/mouse protocol handler initialized
[    3.251026] IR XMP protocol handler initialized
[    3.279618] tmp102 0-0048: error reading config register
[    3.285083] tmp102: probe of 0-0048 failed with error -121
[    3.293463] sdhci: Secure Digital Host Controller Interface driver
[    3.299697] sdhci: Copyright(c) Pierre Ossman
[    3.304597] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.311336] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.317372] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.323965] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.333158] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.342262] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.348995] sdhci-omap 4809c000.mmc: lookup for GPIO cd failed
[    3.354871] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.360919] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.367479] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.376667] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.385766] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.392508] sdhci-omap 4809c000.mmc: lookup for GPIO wp failed
[    3.398516] sdhci-omap 4809c000.mmc: 4809c000.mmc supply vqmmc not found, using dummy regulator
[    3.407943] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led0[0]' - status (0)
[    3.416976] no flags found for gpios
[    3.420686] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led1[0]' - status (0)
[    3.429706] no flags found for gpios
[    3.433386] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led2[0]' - status (0)
[    3.442415] no flags found for gpios
[    3.446099] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led3[0]' - status (0)
[    3.455120] no flags found for gpios
[    3.459168] ledtrig-cpu: registered to indicate activity on CPUs
[    3.469070] NET: Registered protocol family 10
[    3.474377] Segment Routing with IPv6
[    3.478106] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.484501] NET: Registered protocol family 17
[    3.489146] Key type dns_resolver registered
[    3.493561] omap_voltage_late_init: Voltage driver support not added
[    3.499964] Power Management for TI OMAP4+ devices.
[    3.505103] Registering SWP/SWPB emulation handler
[    3.522115] dmm 4e000000.dmm: workaround for errata i878 in use
[    3.529673] dmm 4e000000.dmm: initialized all PAT entries
[    3.536108] tpd12s015 encoder: failed to find video source
[    3.541923] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    3.550646] connector-hdmi connector: failed to find video source
[    3.557064] panel-dpi display: GPIO lookup for consumer enable
[    3.562944] panel-dpi display: using device tree for GPIO lookup
[    3.569004] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    3.578466] panel-dpi display: GPIO lookup for consumer reset
[    3.584252] panel-dpi display: using device tree for GPIO lookup
[    3.590300] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    3.598952] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    3.607529] panel-dpi display: using lookup tables for GPIO lookup
[    3.613750] panel-dpi display: lookup for GPIO reset failed
[    3.619364] panel-dpi display: display supply vcc not found, using dummy regulator
[    3.627099] panel-dpi display: failed to find video source
[    3.644051] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.650125] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.656687] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.665902] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.675013] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.681778] sdhci-omap 4809c000.mmc: lookup for GPIO cd failed
[    3.687642] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.693689] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.700261] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.709434] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.718533] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.725276] sdhci-omap 4809c000.mmc: lookup for GPIO wp failed
[    3.731325] sdhci-omap 4809c000.mmc: 4809c000.mmc supply vqmmc not found, using dummy regulator
[    3.740946] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER5[0]' - status (0)
[    3.750614] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER4[0]' - status (0)
[    3.760256] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER3[0]' - status (0)
[    3.769891] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER2[0]' - status (0)
[    3.779517] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER1[0]' - status (0)
[    3.789260] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    3.796765] tpd12s015 encoder: failed to find video source
[    3.801273] hctosys: unable to open rtc device (rtc0)
[    3.802142] vmmcwl_fixed: disabling
[    3.802150] vdd_3v3: disabling
[    3.802154] aic_dvdd_fixed: disabling
[    3.802162] pbias_mmc_omap5: disabling
[    3.802173] ALSA device list:
[    3.802177]   No soundcards found.
[    3.828088] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[   3.836835] connector-hdmi connector: failed to find video source
[    3.843195] panel-dpi display: GPIO lookup for consumer enable
[    3.849057] panel-dpi display: using device tree for GPIO lookup
[    3.855131] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    3.864591] panel-dpi display: GPIO lookup for consumer reset
[    3.870377] panel-dpi display: using device tree for GPIO lookup
[    3.876413] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    3.885081] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    3.893661] panel-dpi display: using lookup tables for GPIO lookup
[    3.899884] panel-dpi display: lookup for GPIO reset failed
[    3.905496] panel-dpi display: display supply vcc not found, using dummy regulator
[    3.913222] panel-dpi display: failed to find video source
[    3.920137] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.926175] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.932757] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.941952] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.951059] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.957791] sdhci-omap 4809c000.mmc: lookup for GPIO cd failed
[    3.963668] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.969719] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.976277] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.985469] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.994567] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    4.001313] sdhci-omap 4809c000.mmc: lookup for GPIO wp failed
[    4.007332] sdhci-omap 4809c000.mmc: 4809c000.mmc supply vqmmc not found, using dummy regulator
[    4.016646] VFS: Cannot open root device "PARTUUID=a464469c-02" or unknown-block(0,0): error -6
[    4.025405] Please append a correct "root=" boot option; here are the available partitions:
[    4.033856] 0100           65536 ram0
[    4.033861]  (driver?)
[    4.040008] 0101           65536 ram1
[    4.040013]  (driver?)
[    4.046144] 0102           65536 ram2
[    4.046149]  (driver?)
[    4.052297] 0103           65536 ram3
[    4.052302]  (driver?)
[    4.058430] 0104           65536 ram4
[    4.058435]  (driver?)
[    4.064589] 0105           65536 ram5
[    4.064594]  (driver?)
[    4.070741] 0106           65536 ram6
[    4.070746]  (driver?)
[    4.076874] 0107           65536 ram7
[    4.076879]  (driver?)
[    4.083029] 0108           65536 ram8
[    4.083033]  (driver?)
[    4.089162] 0109           65536 ram9
[    4.089166]  (driver?)
[    4.095362] 010a           65536 ram10
[    4.095367]  (driver?)
[    4.101602] 010b           65536 ram11
[    4.101607]  (driver?)
[    4.107827] 010c           65536 ram12
[    4.107832]  (driver?)
[    4.114063] 010d           65536 ram13
[    4.114068]  (driver?)
[    4.120296] 010e           65536 ram14
[    4.120301]  (driver?)
[    4.126516] 010f           65536 ram15
[    4.126521]  (driver?)
[    4.132756] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
[    4.141067] CPU1: stopping
[    4.143792] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.14.79-gbde58ab01e #1
[    4.150871] Hardware name: Generic DRA74X (Flattened Device Tree)
[    4.156989] Backtrace:
[    4.159460] [<c020b4dc>] (dump_backtrace) from [<c020b7c0>] (show_stack+0x18/0x1c)
[    4.167066]  r7:fa212000 r6:20000193 r5:00000000 r4:c1053d10
[    4.172758] [<c020b7a8>] (show_stack) from [<c09313e8>] (dump_stack+0x90/0xa4)
[    4.180018] [<c0931358>] (dump_stack) from [<c020eaa0>] (handle_IPI+0x1b8/0x1cc)
[    4.187448]  r7:fa212000 r6:00000001 r5:00000000 r4:c0e64b3c
[    4.193135] [<c020e8e8>] (handle_IPI) from [<c02014ac>] (gic_handle_irq+0x7c/0x80)
[    4.200738]  r6:ee8a3f20 r5:fa21200c r4:c1004000
[    4.205379] [<c0201430>] (gic_handle_irq) from [<c020c378>] (__irq_svc+0x58/0x8c)
[    4.212894] Exception stack(0xee8a3f20 to 0xee8a3f68)
[    4.217969] 3f20: 00000001 00000000 fe600000 00000000 ffffe000 c1003cdc c1003c7c 00000000
[    4.226184] 3f40: 00000000 c0e643f8 c1003ce8 ee8a3f7c ee8a3f5c ee8a3f70 c021ffe4 c02087ec
[    4.234395] 3f60: 60000013 ffffffff
[    4.237900]  r9:ee8a2000 r8:00000000 r7:ee8a3f54 r6:ffffffff r5:60000013 r4:c02087ec
[    4.245684] [<c02087c4>] (arch_cpu_idle) from [<c0949bbc>] (default_idle_call+0x28/0x34)
[    4.253815] [<c0949b94>] (default_idle_call) from [<c026b54c>] (do_idle+0x194/0x224)
[    4.261594] [<c026b3b8>] (do_idle) from [<c026b8a0>] (cpu_startup_entry+0x20/0x24)
[    4.269199]  r10:00000000 r9:412fc0f2 r8:80007000 r7:c1058250 r6:00000001 r5:ee8a2000
[    4.277060]  r4:00000084
[    4.279607] [<c026b880>] (cpu_startup_entry) from [<c020e664>] (secondary_start_kernel+0x174/0x180)
[    4.288697] [<c020e4f0>] (secondary_start_kernel) from [<802017ac>] (0x802017ac)
[    4.296124]  r7:c1058250 r6:30c0387d r5:00000000 r4:ae84ab00
[    4.301820] ---[ end Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)

6. I removed mmc-ddr-1_8v, cd-gpios and vqmmc-supply on your advice -  unsuccessful.

▒<debug_uart>
U-Boot SPL 2018.01-00562-g2953657-dirty (Aug 18 2021 - 18:28:18)
DRA752-GP ES2.0
Trying to boot from MMC1
no pinctrl state for default mode
MMC Device 1 not found
*** Warning - No MMC card found, using default environment

<debug_uart>

U-Boot 2018.01-00562-g2953657-dirty (Aug 18 2021 - 18:28:18 +0700)

CPU  : DRA752-GP ES2.0
Model: TI AM5728 MICRAN218 b
Board: UNKNOWN(BeagleBoard X15?) REV UNKNOWN
DRAM:  2 GiB
MMC:   OMAP SD/MMC: 0
MMC Device 1 not found
*** Warning - No MMC card found, using default environment

In:    serial@48020000
Out:   serial@48020000
Err:   serial@48020000
SCSI:  SATA link 0 timeout.
AHCI 0001.0300 32 slots 1 ports 3 Gbps 0x1 impl SATA mode
flags: 64bit ncq stag pm led clo only pmp pio slum part ccc apst
scanning bus for devices...
Found 0 device(s).
Net:   !!! eth_initialize() uclass
!!! eth_common_init()
 !!! miiphy_init()
!!! phy_init()
!!! phy_micrel_ksz90x1_init()
!!! phy_register() driver_name: Micrel ksz9021
!!! phy_register() driver_name: Micrel ksz9031
AAA slave_index:0 reg:1 active_slave:1
AAA slave_index:1 reg:2 active_slave:1
^^^ Save slave 0
^^^ Save slave 1
^^^ in cpsw_eth_ofdata_to_platdata() PHY interface 'rgmii'
^^^ cpsw_slave_setup() slave->regs: 0x48484208
^^^ cpsw_slave_setup() slave->regs: 0x48484308
!!! mdio_register()_1 bus_name: ethernet@48484000
!!! mdio_register()_2 bus_name: ethernet@48484000
??? phy_connect()
??? phy_find_by_mask() mask = 4
??? get_phy_device_by_mask, interface = 7
??? search_for_existing_phy() Fail
??? get_phy_id() busname = ethernet@48484000, addr = 2, devad = -1, phy_id = -1 R1 = 0x2 R2 = 0x3
??? create_phy_by_mask() 2, 0
??? phy_device_create()
!!! phy_probe()
??? phy_connect_dev()

Warning: ethernet@48484000 using MAC address from ROM b0:7e:11:03:13:7b
eth0: ethernet@48484000
Hit any key to stop autoboot1:  0
unable to read ssr
switch to partitions #0, OK
mmc0 is current device
unable to read ssr
SD/MMC found on device 0
** Unable to read file boot.scr **
** Unable to read file uEnv.txt **
unable to read ssr
switch to partitions #0, OK
mmc0 is current device
unable to read ssr
SD/MMC found on device 0
4022784 bytes read in 557 ms (6.9 MiB/s)
147735 bytes read in 85 ms (1.7 MiB/s)
## Flattened Device Tree blob at 88000000
   Booting using the fdt blob at 0x88000000
   Loading Device Tree to 8ffd8000, end 8ffff116 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.79-gbde58ab01e (khrenkov@khrenkov-sitar) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #1 SMP PREEMPT Wed Aug 18 16:43:08 +07 2021
[    0.000000] CPU: ARMv7 Processor [412fc0f2] revision 2 (ARMv7), cr=30c5387d
[    0.000000] CPU: div instructions available: patching division code
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction cache
[    0.000000] OF: fdt: Machine model: TI AM5728 EVM
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000095800000, size 56 MiB
[    0.000000] OF: reserved mem: initialized node ipu2-memory@95800000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x0000000099000000, size 64 MiB
[    0.000000] OF: reserved mem: initialized node dsp1-memory@99000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009d000000, size 32 MiB
[    0.000000] OF: reserved mem: initialized node ipu1-memory@9d000000, compatible id shared-dma-pool
[    0.000000] Reserved memory: created CMA memory pool at 0x000000009f000000, size 8 MiB
[    0.000000] OF: reserved mem: initialized node dsp2-memory@9f000000, compatible id shared-dma-pool
[    0.000000] cma: Reserved 24 MiB at 0x00000000fe400000
[    0.000000] OMAP4: Map 0x00000000ffd00000 to fe600000 for dram barrier
[    0.000000] On node 0 totalpages: 474368
[    0.000000] free_area_init_node: node 0, pgdat c1053d80, node_mem_map eeda2000
[    0.000000]   DMA zone: 1728 pages used for memmap
[    0.000000]   DMA zone: 0 pages reserved
[    0.000000]   DMA zone: 147456 pages, LIFO batch:31
[    0.000000]   HighMem zone: 326912 pages, LIFO batch:31
[    0.000000] DRA752 ES2.0
[    0.000000] percpu: Embedded 15 pages/cpu @eed29000 s31372 r8192 d21876 u61440
[    0.000000] pcpu-alloc: s31372 r8192 d21876 u61440 alloc=15*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 472640
[    0.000000] Kernel command line: console=ttyO2,115200n8 root=PARTUUID=a464469c-02 rw rootfstype=ext4 rootwait
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 1675572K/1897472K available (8192K kernel code, 347K rwdata, 2564K rodata, 2048K init, 282K bss, 33484K reserved, 188416K cma-reserved, 1283072K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc0a00000   (10208 kB)
[    0.000000]       .init : 0xc0e00000 - 0xc1000000   (2048 kB)
[    0.000000]       .data : 0xc1000000 - 0xc1056e98   ( 348 kB)
[    0.000000]        .bss : 0xc1058000 - 0xc109ebe0   ( 283 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Tasks RCU enabled.
[    0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] OMAP clockevent source: timer1 at 32786 Hz
[    0.000000] arch_timer: cp15 timer(s) running at 6.14MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x16af5adb9, max_idle_ns: 440795202250 ns
[    0.000004] sched_clock: 56 bits at 6MHz, resolution 162ns, wraps every 4398046511023ns
[    0.000016] Switching to timer-based delay loop, resolution 162ns
[    0.000353] clocksource: 32k_counter: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 58327039986419 ns
[    0.000362] OMAP clocksource: 32k_counter at 32768 Hz
[    0.000873] Console: colour dummy device 80x30
[    0.000890] WARNING: Your 'console=ttyO2' has been replaced by 'ttyS2'
[    0.000897] This ensures that you still see kernel messages. Please
[    0.000904] update your kernel commandline.
[    0.000926] Calibrating delay loop (skipped), value calculated using timer frequency.. 12.29 BogoMIPS (lpj=61475)
[    0.000942] pid_max: default: 32768 minimum: 301
[    0.001059] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001073] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.001611] CPU: Testing write buffer coherency: ok
[    0.001648] CPU0: Spectre v2: using ICIALLU workaround
[    0.001845] /cpus/cpu@0 missing clock-frequency property
[    0.001864] /cpus/cpu@1 missing clock-frequency property
[    0.001876] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.039855] Setting up static identity map for 0x80200000 - 0x80200060
[    0.059865] Hierarchical SRCU implementation.
[    0.080056] EFI services will not be available.
[    0.099925] smp: Bringing up secondary CPUs ...
[    0.170288] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.170294] CPU1: Spectre v2: using ICIALLU workaround
[    0.170396] smp: Brought up 1 node, 2 CPUs
[    0.170407] SMP: Total of 2 processors activated (24.59 BogoMIPS).
[    0.170415] CPU: All CPU(s) started in HYP mode.
[    0.170422] CPU: Virtualization extensions available.
[    0.170955] devtmpfs: initialized
[    0.191641] random: get_random_u32 called from bucket_table_alloc+0x108/0x230 with crng_init=0
[    0.191888] VFP support v0.3: implementor 41 architecture 4 part 30 variant f rev 0
[    0.192080] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[    0.192096] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.195845] pinctrl core: initialized pinctrl subsystem
[    0.196291] DMI not present or invalid.
[    0.196544] NET: Registered protocol family 16
[    0.197579] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.198521] omap_hwmod: l3_main_2 using broken dt data from ocp
[    0.410453] cpuidle: using governor ladder
[    0.410485] cpuidle: using governor menu
[    0.418935] gpio gpiochip0: (gpio): added GPIO chardev (254:0)
[    0.419002] gpiochip_setup_dev: registered GPIOs 0 to 31 on device: gpiochip0 (gpio)
[    0.419061] OMAP GPIO hardware version 0.1
[    0.419688] gpio gpiochip1: (gpio): added GPIO chardev (254:1)
[    0.419758] gpiochip_setup_dev: registered GPIOs 32 to 63 on device: gpiochip1 (gpio)
[    0.420460] gpio gpiochip2: (gpio): added GPIO chardev (254:2)
[    0.420530] gpiochip_setup_dev: registered GPIOs 64 to 95 on device: gpiochip2 (gpio)
[    0.421192] gpio gpiochip3: (gpio): added GPIO chardev (254:3)
[    0.421257] gpiochip_setup_dev: registered GPIOs 96 to 127 on device: gpiochip3 (gpio)
[    0.421923] gpio gpiochip4: (gpio): added GPIO chardev (254:4)
[    0.421986] gpiochip_setup_dev: registered GPIOs 128 to 159 on device: gpiochip4 (gpio)
[    0.422651] gpio gpiochip5: (gpio): added GPIO chardev (254:5)
[    0.422717] gpiochip_setup_dev: registered GPIOs 160 to 191 on device: gpiochip5 (gpio)
[    0.423376] gpio gpiochip6: (gpio): added GPIO chardev (254:6)
[    0.423448] gpiochip_setup_dev: registered GPIOs 192 to 223 on device: gpiochip6 (gpio)
[    0.424104] gpio gpiochip7: (gpio): added GPIO chardev (254:7)
[    0.424170] gpiochip_setup_dev: registered GPIOs 224 to 255 on device: gpiochip7 (gpio)
[    0.446221] No ATAGs?
[    0.446296] hw-breakpoint: found 5 (+1 reserved) breakpoint and 4 watchpoint registers.
[    0.446309] hw-breakpoint: maximum watchpoint size is 8 bytes.
[    0.446695] omap4_sram_init:Unable to allocate sram needed to handle errata I688
[    0.446705] omap4_sram_init:Unable to get sram pool needed to handle errata I688
[    0.447236] OMAP DMA hardware revision 0.0
[    0.456931] edma 43300000.edma: memcpy is disabled
[    0.460086] edma 43300000.edma: TI EDMA DMA engine driver
[    0.466719] omap-dma-engine 4a056000.dma-controller: OMAP DMA engine driver (LinkedList1/2/3 supported)
[    0.467095] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-mmcwl[0]' - status (0)
[    0.467348] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-com_3v6[0]'
[    0.467763] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-main_12v0[0]'
[    0.467990] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-evm_5v0[0]'
[    0.468041] evm_5v0: supplied by main_12v0
[    0.468296] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-vdd_3v3[0]'
[    0.468469] com_3v6: supplied by evm_5v0
[    0.468620] of_get_named_gpiod_flags: can't parse 'gpio' property of node '/fixedregulator-aic_dvdd[0]'
[    0.468964] of_get_named_gpiod_flags: parsed 'gpio' property of node '/fixedregulator-vtt[0]' - status (0)
[    0.471498] omap-iommu 40d01000.mmu: 40d01000.mmu registered
[    0.471692] omap-iommu 40d02000.mmu: 40d02000.mmu registered
[    0.471932] omap-iommu 58882000.mmu: 58882000.mmu registered
[    0.472166] omap-iommu 55082000.mmu: 55082000.mmu registered
[    0.472519] omap-iommu 41501000.mmu: 41501000.mmu registered
[    0.472730] omap-iommu 41502000.mmu: 41502000.mmu registered
[    0.472984] iommu: Adding device 58820000.ipu to group 1
[    0.473071] iommu: Adding device 55020000.ipu to group 2
[    0.473230] iommu: Adding device 40800000.dsp to group 0
[    0.473491] iommu: Adding device 41000000.dsp to group 3
[    0.475793] omap_i2c 48070000.i2c: bus 0 rev0.12 at 400 kHz
[    0.476288] omap_i2c 48060000.i2c: bus 2 rev0.12 at 400 kHz
[    0.476765] omap_i2c 4807c000.i2c: bus 4 rev0.12 at 400 kHz
[    0.476937] media: Linux media interface: v0.10
[    0.476972] Linux video capture interface: v2.00
[    0.477054] pps_core: LinuxPPS API ver. 1 registered
[    0.477063] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    0.477081] PTP clock support registered
[    0.477109] EDAC MC: Ver: 3.0.0
[    0.477353] dmi: Firmware registration failed.
[    0.477744] omap-mailbox 48840000.mailbox: omap mailbox rev 0x400
[    0.478022] omap-mailbox 48842000.mailbox: omap mailbox rev 0x400
[    0.478342] Advanced Linux Sound Architecture Driver Initialized.
[    0.479036] clocksource: Switched to clocksource arch_sys_counter
[    0.486664] NET: Registered protocol family 2
[    0.487182] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.487246] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.487372] TCP: Hash tables configured (established 8192 bind 8192)
[    0.487442] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.487475] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.487597] NET: Registered protocol family 1
[    0.487878] RPC: Registered named UNIX socket transport module.
[    0.487888] RPC: Registered udp transport module.
[    0.487895] RPC: Registered tcp transport module.
[    0.487903] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.487913] PCI: CLS 0 bytes, default 64
[    0.488798] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    0.488977] hw perfevents: enabled with armv7_cortex_a15 PMU driver, 7 counters available
[    0.490005] workingset: timestamp_bits=14 max_order=19 bucket_order=5
[    0.494070] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[    0.494571] NFS: Registering the id_resolver key type
[    0.494593] Key type id_resolver registered
[    0.494601] Key type id_legacy registered
[    0.494638] ntfs: driver 2.1.32 [Flags: R/O].
[    0.495945] bounce: pool size: 64 pages
[    0.495987] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[    0.495998] io scheduler noop registered
[    0.496007] io scheduler deadline registered
[    0.496097] io scheduler cfq registered (default)
[    0.496107] io scheduler mq-deadline registered
[    0.496115] io scheduler kyber registered
[    0.500506] pinctrl-single 4a003400.pinmux: 282 pins at pa fc003400 size 1128
[    0.503718] dra7-pcie 51000000.pcie: Linked as a consumer to phy-4a094000.pciephy.1
[    0.503877] dra7-pcie 51000000.pcie: GPIO lookup for consumer (null)
[    0.503889] dra7-pcie 51000000.pcie: using device tree for GPIO lookup
[    0.503924] of_get_named_gpiod_flags: parsed 'gpios' property of node '/ocp/axi@0/pcie@51000000[0]' - status (0)
[    0.504089] OF: PCI: host bridge /ocp/axi@0/pcie@51000000 ranges:
[    0.504124] OF: PCI:    IO 0x20003000..0x20012fff -> 0x00000000
[    0.504145] OF: PCI:   MEM 0x20013000..0x2fffffff -> 0x20013000
[    1.504415] dra7-pcie 51000000.pcie: phy link never came up
[    1.504548] dra7-pcie 51000000.pcie: PCI host bridge to bus 0000:00
[    1.504561] pci_bus 0000:00: root bus resource [bus 00-ff]
[    1.504573] pci_bus 0000:00: root bus resource [io  0x0000-0xffff]
[    1.504583] pci_bus 0000:00: root bus resource [mem 0x20013000-0x2fffffff]
[    1.504616] pci 0000:00:00.0: [104c:8888] type 01 class 0x060400
[    1.504650] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit]
[    1.504710] pci 0000:00:00.0: supports D1
[    1.504721] pci 0000:00:00.0: PME# supported from D0 D1 D3hot
[    1.504906] PCI: bus0: Fast back to back transfers disabled
[    1.504995] PCI: bus1: Fast back to back transfers enabled
[    1.505032] pci 0000:00:00.0: BAR 0: assigned [mem 0x20100000-0x201fffff 64bit]
[    1.505051] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
[    1.505358] pcieport 0000:00:00.0: Signaling PME with IRQ 167
[    1.505481] pcieport 0000:00:00.0: AER enabled with IRQ 167
[    1.506241] pwm-backlight backlight: GPIO lookup for consumer enable
[    1.506252] pwm-backlight backlight: using device tree for GPIO lookup
[    1.506265] of_get_named_gpiod_flags: can't parse 'enable-gpios' property of node '/backlight[0]'
[    1.506276] of_get_named_gpiod_flags: can't parse 'enable-gpio' property of node '/backlight[0]'
[    1.506285] pwm-backlight backlight: using lookup tables for GPIO lookup
[    1.506295] pwm-backlight backlight: lookup for GPIO enable failed
[    1.506316] pwm-backlight backlight: backlight supply power not found, using dummy regulator
[    1.551067] Serial: 8250/16550 driver, 10 ports, IRQ sharing disabled
[    1.553705] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 45, base_baud = 3000000) is a 8250
[    2.860757] console [ttyS2] enabled
[    2.865074] 48422000.serial: ttyS7 at MMIO 0x48422000 (irq = 46, base_baud = 3000000) is a 8250
[    2.875684] omap_rng 48090000.rng: Random Number Generator ver. 20
[    2.884129] tpd12s015 encoder: failed to find video source
[    2.890315] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    2.899018] connector-hdmi connector: failed to find video source
[    2.905255] panel-dpi display: GPIO lookup for consumer enable
[    2.911136] panel-dpi display: using device tree for GPIO lookup
[    2.917193] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    2.926655] panel-dpi display: GPIO lookup for consumer reset
[    2.932445] panel-dpi display: using device tree for GPIO lookup
[    2.938480] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    2.947155] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    2.955733] panel-dpi display: using lookup tables for GPIO lookup
[    2.961957] panel-dpi display: lookup for GPIO reset failed
[    2.967572] panel-dpi display: display supply vcc not found, using dummy regulator
[    2.975296] panel-dpi display: failed to find video source
[    2.990902] brd: module loaded
[    2.999370] loop: module loaded
[    3.005405] mdio_bus fixed-0: GPIO lookup for consumer reset
[    3.011120] mdio_bus fixed-0: using lookup tables for GPIO lookup
[    3.017244] mdio_bus fixed-0: lookup for GPIO reset failed
[    3.022807] libphy: Fixed MDIO Bus: probed
[    3.029523] mdio_bus 48485000.mdio: GPIO lookup for consumer reset
[    3.035734] mdio_bus 48485000.mdio: using device tree for GPIO lookup
[    3.042236] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    3.053350] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/ocp/ethernet@48484000/mdio@48485000[0]'
[    3.064373] mdio_bus 48485000.mdio: using lookup tables for GPIO lookup
[    3.071038] mdio_bus 48485000.mdio: lookup for GPIO reset failed
[    3.129094] davinci_mdio 48485000.mdio: davinci mdio revision 1.6, bus freq 1000000
[    3.136787] libphy: 48485000.mdio: probed
[    3.145752] davinci_mdio 48485000.mdio: phy[0]: device 48485000.mdio:00, driver Micrel KSZ9031 Gigabit PHY
[    3.155495] davinci_mdio 48485000.mdio: phy[2]: device 48485000.mdio:02, driver Micrel KSZ9031 Gigabit PHY
[    3.165778] cpsw 48484000.ethernet: Detected MACID = b0:7e:11:03:13:7b
[    3.172416] cpsw 48484000.ethernet: initialized cpsw ale version 1.4
[    3.178800] cpsw 48484000.ethernet: ALE Table size 1024
[    3.184099] cpsw 48484000.ethernet: device node lookup for pps timer failed
[    3.191149] cpsw 48484000.ethernet: cpts: overflow check period 500 (jiffies)
[    3.199002] cpsw 48484000.ethernet: cpsw: Detected MACID = b0:7e:11:03:13:7b
[    3.207204] i2c /dev entries driver
[    3.211623] IR NEC protocol handler initialized
[    3.216175] IR RC5(x/sz) protocol handler initialized
[    3.221273] IR RC6 protocol handler initialized
[    3.225821] IR JVC protocol handler initialized
[    3.230388] IR Sony protocol handler initialized
[    3.235025] IR SANYO protocol handler initialized
[    3.239949] IR Sharp protocol handler initialized
[    3.244674] IR MCE Keyboard/mouse protocol handler initialized
[    3.250548] IR XMP protocol handler initialized
[    3.279126] tmp102 0-0048: error reading config register
[    3.284590] tmp102: probe of 0-0048 failed with error -121
[    3.293016] sdhci: Secure Digital Host Controller Interface driver
[    3.299251] sdhci: Copyright(c) Pierre Ossman
[    3.304153] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.310896] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.316932] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.323524] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.332720] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.341824] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.348557] sdhci-omap 4809c000.mmc: lookup for GPIO cd failed
[    3.354435] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.360482] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.367042] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.376230] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.385329] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.392074] sdhci-omap 4809c000.mmc: lookup for GPIO wp failed
[    3.398097] sdhci-omap 4809c000.mmc: failed to set system capabilities
[    3.405145] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led0[0]' - status (0)
[    3.414179] no flags found for gpios
[    3.417872] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led1[0]' - status (0)
[    3.426892] no flags found for gpios
[    3.430590] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led2[0]' - status (0)
[    3.439613] no flags found for gpios
[    3.443296] of_get_named_gpiod_flags: parsed 'gpios' property of node '/leds/led3[0]' - status (0)
[    3.452317] no flags found for gpios
[    3.456360] ledtrig-cpu: registered to indicate activity on CPUs
[    3.466260] NET: Registered protocol family 10
[    3.471569] Segment Routing with IPv6
[    3.475297] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.481693] NET: Registered protocol family 17
[    3.486335] Key type dns_resolver registered
[    3.490760] omap_voltage_late_init: Voltage driver support not added
[    3.497144] Power Management for TI OMAP4+ devices.
[    3.502300] Registering SWP/SWPB emulation handler
[    3.519321] dmm 4e000000.dmm: workaround for errata i878 in use
[    3.526882] dmm 4e000000.dmm: initialized all PAT entries
[    3.533352] tpd12s015 encoder: failed to find video source
[    3.539177] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    3.547879] connector-hdmi connector: failed to find video source
[    3.554324] panel-dpi display: GPIO lookup for consumer enable
[    3.560202] panel-dpi display: using device tree for GPIO lookup
[    3.566261] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    3.575720] panel-dpi display: GPIO lookup for consumer reset
[    3.581507] panel-dpi display: using device tree for GPIO lookup
[    3.587542] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    3.596207] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    3.604781] panel-dpi display: using lookup tables for GPIO lookup
[    3.611002] panel-dpi display: lookup for GPIO reset failed
[    3.616615] panel-dpi display: display supply vcc not found, using dummy regulator
[    3.624353] panel-dpi display: failed to find video source
[    3.641300] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.647337] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.653936] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.663152] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.672262] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.678993] sdhci-omap 4809c000.mmc: lookup for GPIO cd failed
[    3.684888] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.690938] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.697498] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.706685] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.715785] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.722531] sdhci-omap 4809c000.mmc: lookup for GPIO wp failed
[    3.728584] sdhci-omap 4809c000.mmc: failed to set system capabilities
[    3.735831] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER5[0]' - status (0)
[    3.745495] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER4[0]' - status (0)
[    3.755136] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER3[0]' - status (0)
[    3.764771] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER2[0]' - status (0)
[    3.774418] of_get_named_gpiod_flags: parsed 'gpios' property of node '/gpio_keys/USER1[0]' - status (0)
[    3.784152] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[    3.791656] tpd12s015 encoder: failed to find video source
[    3.797433] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[    3.800783] hctosys: unable to open rtc device (rtc0)
[    3.801648] vmmcwl_fixed: disabling
[    3.801655] vdd_3v3: disabling
[    3.801660] aic_dvdd_fixed: disabling
[    3.801668] pbias_mmc_omap5: disabling
[    3.801680] ALSA device list:
[    3.801683]   No soundcards found.
[    3.831638] connector-hdmi connector: failed to find video source
[    3.838122] panel-dpi display: GPIO lookup for consumer enable
[    3.844005] panel-dpi display: using device tree for GPIO lookup
[    3.850095] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    3.859554] panel-dpi display: GPIO lookup for consumer reset
[    3.865327] panel-dpi display: using device tree for GPIO lookup
[    3.871384] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    3.880052] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    3.888615] panel-dpi display: using lookup tables for GPIO lookup
[    3.894838] panel-dpi display: lookup for GPIO reset failed
[    3.900464] panel-dpi display: display supply vcc not found, using dummy regulator
[    3.908172] panel-dpi display: failed to find video source
[    3.915083] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.921150] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.927713] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.936907] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.946009] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.952763] sdhci-omap 4809c000.mmc: lookup for GPIO cd failed
[    3.958624] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.964672] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.971246] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.980436] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.989536] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.996268] sdhci-omap 4809c000.mmc: lookup for GPIO wp failed
[    4.002321] sdhci-omap 4809c000.mmc: failed to set system capabilities
[    4.009211] Waiting for root device PARTUUID=a464469c-02...

Result dts:

/dts-v1/;

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	compatible = "ti,am5728-evm", "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
	interrupt-parent = <0x1>;
	model = "TI AM5728 EVM";

	fixedregulator-mmcwl {
		phandle = <0x24a>;
		enable-active-high;
		gpio = <0x1a3 0x8 0x0>;
		regulator-max-microvolt = <0x1b7740>;
		regulator-min-microvolt = <0x1b7740>;
		regulator-name = "vmmcwl_fixed";
		compatible = "regulator-fixed";
	};

	fixedregulator-com_3v6 {
		phandle = <0x249>;
		regulator-boot-on;
		regulator-always-on;
		vin-supply = <0x23f>;
		regulator-max-microvolt = <0x36ee80>;
		regulator-min-microvolt = <0x36ee80>;
		regulator-name = "com_3v6";
		compatible = "regulator-fixed";
	};

	backlight {
		phandle = <0x246>;
		pwms = <0x213 0x0 0xc350 0x0>;
		default-brightness-level = <0x8>;
		brightness-levels = <0x0 0xf3 0xf5 0xf7 0xf9 0xfb 0xfc 0xfd 0xff>;
		compatible = "pwm-backlight";
	};

	display {
		phandle = <0x24b>;
		label = "lcd";
		enable-gpios = <0xaf 0x5 0x0>;
		backlight = <0x246>;
		compatible = "osddisplays,osd070t1718-19ts", "panel-dpi";

		port {

			endpoint {
				phandle = <0x248>;
				remote-endpoint = <0x247>;
			};
		};

		panel-timing {
			vsync-len = <0xd>;
			vsync-active = <0x0>;
			vfront-porch = <0x16>;
			vback-porch = <0xa>;
			vactive = <0x1e0>;
			pixelclk-active = <0x1>;
			hsync-len = <0x1e>;
			hsync-active = <0x0>;
			hfront-porch = <0xd2>;
			hback-porch = <0x10>;
			hactive = <0x320>;
			de-active = <0x1>;
			clock-frequency = <0x1f78a40>;
		};
	};

	gpio_keys {
		autorepeat;
		#size-cells = <0x0>;
		#address-cells = <0x1>;
		compatible = "gpio-keys";

		USER5 {
			linux,code = <0x66>;
			label = "Home";
			gpios = <0xaf 0x14 0x1>;
		};

		USER4 {
			linux,code = <0x6a>;
			label = "Right";
			gpios = <0xaf 0x18 0x1>;
		};

		USER3 {
			linux,code = <0x69>;
			label = "Left";
			gpios = <0xaf 0x1c 0x1>;
		};

		USER2 {
			linux,code = <0x6c>;
			label = "Down";
			gpios = <0xaf 0x19 0x1>;
		};

		USER1 {
			linux,code = <0x67>;
			label = "Up";
			gpios = <0xaf 0x17 0x1>;
		};
	};

	chosen {
		stdout-path = "/ocp/serial@48020000";
	};

	aliases {
		display1 = "/connector";
		i2c0 = "/ocp/i2c@48070000";
		i2c1 = "/ocp/i2c@48072000";
		i2c2 = "/ocp/i2c@48060000";
		i2c3 = "/ocp/i2c@4807a000";
		i2c4 = "/ocp/i2c@4807c000";
		serial0 = "/ocp/serial@4806a000";
		serial1 = "/ocp/serial@4806c000";
		serial2 = "/ocp/serial@48020000";
		serial3 = "/ocp/serial@4806e000";
		serial4 = "/ocp/serial@48066000";
		serial5 = "/ocp/serial@48068000";
		serial6 = "/ocp/serial@48420000";
		serial7 = "/ocp/serial@48422000";
		serial8 = "/ocp/serial@48424000";
		serial9 = "/ocp/serial@4ae2b000";
		ethernet0 = "/ocp/ethernet@48484000/slave@48480200";
		ethernet1 = "/ocp/ethernet@48484000/slave@48480300";
		d_can0 = "/ocp/can@4ae3c000";
		d_can1 = "/ocp/can@48480000";
		spi0 = "/ocp/qspi@4b300000";
		rproc0 = "/ocp/ipu@58820000";
		rproc1 = "/ocp/ipu@55020000";
		rproc2 = "/ocp/dsp@40800000";
		rproc3 = "/ocp/dsp@41000000";
		rtc0 = "/ocp/i2c@48060000/rtc@6f";
		rtc1 = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
		rtc2 = "/ocp/rtc@48838000";
		display0 = "/display";
		sound1 = "/ocp/dss@58000000/encoder@58060000";
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <0x1 0xd 0x308 0x1 0xe 0x308 0x1 0xb 0x308 0x1 0xa 0x308>;
		interrupt-parent = <0x2>;
	};

	interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x0 0x48211000 0x0 0x1000 0x0 0x48212000 0x0 0x2000 0x0 0x48214000 0x0 0x2000 0x0 0x48216000 0x0 0x2000>;
		interrupts = <0x1 0x9 0x304>;
		interrupt-parent = <0x2>;
		phandle = <0x2>;
	};

	interrupt-controller@48281000 {
		compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		reg = <0x0 0x48281000 0x0 0x1000>;
		interrupt-parent = <0x2>;
		phandle = <0x8>;
	};

	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x0>;
			operating-points-v2 = <0x3>;
			clocks = <0x4>;
			clock-names = "cpu";
			clock-latency = <0x493e0>;
			cooling-min-level = <0x0>;
			cooling-max-level = <0x2>;
			#cooling-cells = <0x2>;
			vbb-supply = <0x5>;
			vdd-supply = <0x6>;
			voltage-tolerance = <0x1>;
			phandle = <0x121>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0x1>;
			operating-points-v2 = <0x3>;
		};
	};

	opp-table {
		compatible = "operating-points-v2-ti-cpu";
		syscon = <0x7>;
		opp-shared;
		phandle = <0x3>;

		opp_nom-1000000000 {
			opp-hz = <0x0 0x3b9aca00>;
			opp-microvolt = <0x102ca0 0xcf850 0x118c30 0x102ca0 0xcf850 0x118c30>;
			opp-supported-hw = <0xff 0x1>;
			opp-suspend;
		};

		opp_od-1176000000 {
			opp-hz = <0x0 0x46185600>;
			opp-microvolt = <0x11b340 0xd8108 0x11b340 0x11b340 0xd8108 0x11b340>;
			opp-supported-hw = <0xff 0x2>;
		};

		opp_high@1500000000 {
			opp-hz = <0x0 0x59682f00>;
			opp-microvolt = <0x127690 0xe7ef0 0x1312d0 0x127690 0xe7ef0 0x1312d0>;
			opp-supported-hw = <0xff 0x4>;
		};
	};

	soc {
		compatible = "ti,omap-infra";

		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	ocp {
		compatible = "ti,dra7-l3-noc", "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges = <0x0 0x0 0x0 0xc0000000>;
		ti,hwmods = "l3_main_1", "l3_main_2";
		reg = <0x0 0x44000000 0x0 0x1000000 0x0 0x45000000 0x0 0x1000>;
		interrupts-extended = <0x1 0x0 0x4 0x4 0x8 0x0 0xa 0x4>;

		l4@4a000000 {
			compatible = "ti,dra7-l4-cfg", "simple-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4a000000 0x22c000>;
			phandle = <0x133>;

			scm@2000 {
				compatible = "ti,dra7-scm-core", "simple-bus";
				reg = <0x2000 0x2000>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges = <0x0 0x2000 0x2000>;
				phandle = <0x134>;

				scm_conf@0 {
					compatible = "syscon", "simple-bus";
					reg = <0x0 0x1400>;
					#address-cells = <0x1>;
					#size-cells = <0x1>;
					ranges = <0x0 0x0 0x1400>;
					phandle = <0x9>;

					pbias_regulator@e00 {
						compatible = "ti,pbias-dra7", "ti,pbias-omap";
						reg = <0xe00 0x4>;
						syscon = <0x9>;
						phandle = <0x135>;

						pbias_mmc_omap5 {
							regulator-name = "pbias_mmc_omap5";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x325aa0>;
							phandle = <0xd1>;
						};
					};

					clocks {
						#address-cells = <0x1>;
						#size-cells = <0x0>;
						phandle = <0x136>;

						dss_deshdcp_clk@558 {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0xa>;
							ti,bit-shift = <0x0>;
							reg = <0x558>;
							phandle = <0x137>;
						};

						ehrpwm0_tbclk@558 {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0xb>;
							ti,bit-shift = <0x14>;
							reg = <0x558>;
							phandle = <0x115>;
						};

						ehrpwm1_tbclk@558 {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0xb>;
							ti,bit-shift = <0x15>;
							reg = <0x558>;
							phandle = <0x116>;
						};

						ehrpwm2_tbclk@558 {
							#clock-cells = <0x0>;
							compatible = "ti,gate-clock";
							clocks = <0xb>;
							ti,bit-shift = <0x16>;
							reg = <0x558>;
							phandle = <0x117>;
						};

						sys_32k_ck {
							#clock-cells = <0x0>;
							compatible = "ti,mux-clock";
							clocks = <0xc 0xd 0xd 0xd>;
							ti,bit-shift = <0x8>;
							reg = <0x6c4>;
							phandle = <0x51>;
						};
					};
				};

				pinmux@1400 {
					compatible = "ti,dra7-padconf", "pinctrl-single";
					reg = <0x1400 0x468>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					#pinctrl-cells = <0x1>;
					#interrupt-cells = <0x1>;
					interrupt-controller;
					pinctrl-single,register-width = <0x20>;
					pinctrl-single,function-mask = <0x3fffffff>;
					phandle = <0xb5>;

					mmc1_pins_default {
						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
						phandle = <0xd2>;
					};

					mmc1_pins_default_no_clk_pu {
						pinctrl-single,pins = <0x354 0x40000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
						phandle = <0x138>;
					};

					mmc1_pins_sdr12 {
						pinctrl-single,pins = <0x354 0x60000 0x358 0x60000 0x35c 0x60000 0x360 0x60000 0x364 0x60000 0x368 0x60000>;
						phandle = <0xd4>;
					};

					mmc1_pins_hs {
						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
						phandle = <0xd3>;
					};

					mmc1_pins_sdr25 {
						pinctrl-single,pins = <0x354 0x601b0 0x358 0x601b0 0x35c 0x601b0 0x360 0x601b0 0x364 0x601b0 0x368 0x601b0>;
						phandle = <0xd5>;
					};

					mmc1_pins_sdr50 {
						pinctrl-single,pins = <0x354 0x601a0 0x358 0x601a0 0x35c 0x601a0 0x360 0x601a0 0x364 0x601a0 0x368 0x601a0>;
						phandle = <0xd6>;
					};

					mmc1_pins_ddr50 {
						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
						phandle = <0xd7>;
					};

					mmc1_pins_sdr104 {
						pinctrl-single,pins = <0x354 0x60100 0x358 0x60100 0x35c 0x60100 0x360 0x60100 0x364 0x60100 0x368 0x60100>;
						phandle = <0xd9>;
					};

					mmc2_pins_default {
						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
						phandle = <0xdb>;
					};

					mmc2_pins_hs {
						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
						phandle = <0xdc>;
					};

					mmc2_pins_ddr_3_3v_rev11 {
						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
						phandle = <0x139>;
					};

					mmc2_pins_ddr_1_8v_rev11 {
						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
						phandle = <0x13a>;
					};

					mmc2_pins_ddr_rev20 {
						pinctrl-single,pins = <0x9c 0x60001 0xb0 0x60001 0xa0 0x60001 0xa4 0x60001 0xa8 0x60001 0xac 0x60001 0x8c 0x60001 0x90 0x60001 0x94 0x60001 0x98 0x60001>;
						phandle = <0xdd>;
					};

					mmc2_pins_hs200 {
						pinctrl-single,pins = <0x9c 0x60101 0xb0 0x60101 0xa0 0x60101 0xa4 0x60101 0xa8 0x60101 0xac 0x60101 0x8c 0x60101 0x90 0x60101 0x94 0x60101 0x98 0x60101>;
						phandle = <0x13b>;
					};

					mmc4_pins_default {
						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
						phandle = <0x13c>;
					};

					mmc4_pins_hs {
						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
						phandle = <0x13d>;
					};

					mmc3_pins_default {
						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
						phandle = <0x13e>;
					};

					mmc3_pins_hs {
						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
						phandle = <0x13f>;
					};

					mmc3_pins_sdr12 {
						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
						phandle = <0x140>;
					};

					mmc3_pins_sdr25 {
						pinctrl-single,pins = <0x37c 0x60000 0x380 0x60000 0x384 0x60000 0x388 0x60000 0x38c 0x60000 0x390 0x60000>;
						phandle = <0x141>;
					};

					mmc3_pins_sdr50 {
						pinctrl-single,pins = <0x37c 0x60100 0x380 0x60100 0x384 0x60100 0x388 0x60100 0x38c 0x60100 0x390 0x60100>;
						phandle = <0x142>;
					};

					mmc4_pins_sdr12 {
						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
						phandle = <0x143>;
					};

					mmc4_pins_sdr25 {
						pinctrl-single,pins = <0x3e8 0x60103 0x3ec 0x60103 0x3f0 0x60103 0x3f4 0x60103 0x3f8 0x60103 0x3fc 0x60103>;
						phandle = <0x144>;
					};
				};

				scm_conf@1c04 {
					compatible = "syscon";
					reg = <0x1c04 0x20>;
					#syscon-cells = <0x2>;
					phandle = <0xae>;
				};

				scm_conf@1c24 {
					compatible = "syscon";
					reg = <0x1c24 0x24>;
					phandle = <0xac>;
				};

				dma-router@b78 {
					compatible = "ti,dra7-dma-crossbar";
					reg = <0xb78 0xfc>;
					#dma-cells = <0x1>;
					dma-requests = <0xcd>;
					ti,dma-safe-map = <0x0>;
					dma-masters = <0xe>;
					phandle = <0xb4>;
				};

				dma-router@c78 {
					compatible = "ti,dra7-dma-crossbar";
					reg = <0xc78 0x7c>;
					#dma-cells = <0x2>;
					dma-requests = <0xcc>;
					ti,dma-safe-map = <0x0>;
					dma-masters = <0xf>;
					phandle = <0xf5>;
				};
			};

			cm_core_aon@5000 {
				compatible = "ti,dra7-cm-core-aon";
				reg = <0x5000 0x2000>;
				phandle = <0x145>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					phandle = <0x146>;

					atl_clkin0_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x10>;
						phandle = <0x44>;
					};

					atl_clkin1_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x10>;
						phandle = <0x43>;
					};

					atl_clkin2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x10>;
						phandle = <0x42>;
					};

					atl_clkin3_ck {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-atl-clock";
						clocks = <0x10>;
						phandle = <0x41>;
					};

					hdmi_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x30>;
					};

					mlb_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0xa8>;
					};

					mlbp_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0xa9>;
					};

					pciesref_acs_clk_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x5f5e100>;
						phandle = <0x5b>;
					};

					ref_clkin0_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x46>;
					};

					ref_clkin1_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x47>;
					};

					ref_clkin2_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x48>;
					};

					ref_clkin3_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x49>;
					};

					rmii_clk_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x72>;
					};

					sdvenc_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x147>;
					};

					secure_32k_clk_src_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x8000>;
						phandle = <0x92>;
					};

					sys_clk32_crystal_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x8000>;
						phandle = <0xc>;
					};

					sys_clk32_pseudo_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x11>;
						clock-mult = <0x1>;
						clock-div = <0x262>;
						phandle = <0xd>;
					};

					virt_12000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0xb71b00>;
						phandle = <0x82>;
					};

					virt_13000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0xc65d40>;
						phandle = <0x148>;
					};

					virt_16800000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1005900>;
						phandle = <0x84>;
					};

					virt_19200000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x124f800>;
						phandle = <0x85>;
					};

					virt_20000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1312d00>;
						phandle = <0x83>;
					};

					virt_26000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x18cba80>;
						phandle = <0x86>;
					};

					virt_27000000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x19bfcc0>;
						phandle = <0x87>;
					};

					virt_38400000_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x249f000>;
						phandle = <0x88>;
					};

					sys_clkin2 {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x1588800>;
						phandle = <0x45>;
					};

					usb_otg_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x8f>;
					};

					video1_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x3a>;
					};

					video1_m2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x2f>;
					};

					video2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x3b>;
					};

					video2_m2_clkin_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x2e>;
					};

					dpll_abe_ck@1e0 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-m4xen-clock";
						clocks = <0x12 0x13>;
						reg = <0x1e0 0x1e4 0x1ec 0x1e8>;
						assigned-clocks = <0x14>;
						assigned-clock-rates = <0x2faf080>;
						phandle = <0x14>;
					};

					dpll_abe_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x14>;
						phandle = <0x15>;
					};

					dpll_abe_m2x2_ck@1f0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x15>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x16>;
					};

					abe_clk@108 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x16>;
						ti,max-div = <0x4>;
						reg = <0x108>;
						ti,index-power-of-two;
						phandle = <0x8a>;
					};

					dpll_abe_m2_ck@1f0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x14>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x70>;
					};

					dpll_abe_m3x2_ck@1f4 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x15>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1f4>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x17>;
					};

					dpll_core_byp_mux@12c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x12c>;
						phandle = <0x18>;
					};

					dpll_core_ck@120 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-core-clock";
						clocks = <0x11 0x18>;
						reg = <0x120 0x124 0x12c 0x128>;
						phandle = <0x19>;
					};

					dpll_core_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x19>;
						phandle = <0x1a>;
					};

					dpll_core_h12x2_ck@13c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x13c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x1b>;
					};

					mpu_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x1c>;
					};

					dpll_mpu_ck@160 {
						#clock-cells = <0x0>;
						compatible = "ti,omap5-mpu-dpll-clock";
						clocks = <0x11 0x1c>;
						reg = <0x160 0x164 0x16c 0x168>;
						phandle = <0x4>;
					};

					dpll_mpu_m2_ck@170 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x4>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x170>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x1d>;
					};

					mpu_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1d>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x96>;
					};

					dsp_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x1e>;
					};

					dpll_dsp_byp_mux@240 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x1e>;
						ti,bit-shift = <0x17>;
						reg = <0x240>;
						phandle = <0x1f>;
					};

					dpll_dsp_ck@234 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x1f>;
						reg = <0x234 0x238 0x240 0x23c>;
						assigned-clocks = <0x20>;
						assigned-clock-rates = <0x23c34600>;
						phandle = <0x20>;
					};

					dpll_dsp_m2_ck@244 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x20>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x244>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x21>;
						assigned-clock-rates = <0x23c34600>;
						phandle = <0x21>;
					};

					iva_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x22>;
					};

					dpll_iva_byp_mux@1ac {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x22>;
						ti,bit-shift = <0x17>;
						reg = <0x1ac>;
						phandle = <0x23>;
					};

					dpll_iva_ck@1a0 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x23>;
						reg = <0x1a0 0x1a4 0x1ac 0x1a8>;
						assigned-clocks = <0x24>;
						assigned-clock-rates = <0x45707d40>;
						phandle = <0x24>;
					};

					dpll_iva_m2_ck@1b0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x24>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x1b0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x25>;
						assigned-clock-rates = <0x17257f16>;
						phandle = <0x25>;
					};

					iva_dclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x25>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x98>;
					};

					dpll_gpu_byp_mux@2e4 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x2e4>;
						phandle = <0x26>;
					};

					dpll_gpu_ck@2d8 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x26>;
						reg = <0x2d8 0x2dc 0x2e4 0x2e0>;
						assigned-clocks = <0x27>;
						assigned-clock-rates = <0x4c1d7940>;
						phandle = <0x27>;
					};

					dpll_gpu_m2_ck@2e8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x27>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2e8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x28>;
						assigned-clock-rates = <0x195f286b>;
						phandle = <0x28>;
					};

					dpll_core_m2_ck@130 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x19>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x130>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x29>;
					};

					core_dpll_out_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x29>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9a>;
					};

					dpll_ddr_byp_mux@21c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x21c>;
						phandle = <0x2a>;
					};

					dpll_ddr_ck@210 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x2a>;
						reg = <0x210 0x214 0x21c 0x218>;
						phandle = <0x2b>;
					};

					dpll_ddr_m2_ck@220 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x2b>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x220>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x8c>;
					};

					dpll_gmac_byp_mux@2b4 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x17>;
						ti,bit-shift = <0x17>;
						reg = <0x2b4>;
						phandle = <0x2c>;
					};

					dpll_gmac_ck@2a8 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x2c>;
						reg = <0x2a8 0x2ac 0x2b4 0x2b0>;
						phandle = <0x2d>;
					};

					dpll_gmac_m2_ck@2b8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x2d>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2b8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x8d>;
					};

					video2_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2e>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9c>;
					};

					video1_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x2f>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9d>;
					};

					hdmi_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x30>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9e>;
					};

					per_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x17>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x5f>;
					};

					usb_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x17>;
						clock-mult = <0x1>;
						clock-div = <0x3>;
						phandle = <0x63>;
					};

					eve_dpll_hs_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x1b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x31>;
					};

					dpll_eve_byp_mux@290 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x31>;
						ti,bit-shift = <0x17>;
						reg = <0x290>;
						phandle = <0x32>;
					};

					dpll_eve_ck@284 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x32>;
						reg = <0x284 0x288 0x290 0x28c>;
						phandle = <0x33>;
					};

					dpll_eve_m2_ck@294 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x33>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x294>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x34>;
					};

					eve_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x34>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0xa7>;
					};

					dpll_core_h13x2_ck@140 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x140>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x149>;
					};

					dpll_core_h14x2_ck@144 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x144>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x73>;
					};

					dpll_core_h22x2_ck@154 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x154>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x3c>;
					};

					dpll_core_h23x2_ck@158 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x158>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x81>;
					};

					dpll_core_h24x2_ck@15c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x1a>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x15c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x10c>;
					};

					dpll_ddr_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x2b>;
						phandle = <0x35>;
					};

					dpll_ddr_h11x2_ck@228 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x35>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x228>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x14a>;
					};

					dpll_dsp_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x20>;
						phandle = <0x36>;
					};

					dpll_dsp_m3x2_ck@248 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x36>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x248>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						assigned-clocks = <0x37>;
						assigned-clock-rates = <0x17d78400>;
						phandle = <0x37>;
					};

					dpll_gmac_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x2d>;
						phandle = <0x38>;
					};

					dpll_gmac_h11x2_ck@2c0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x38>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c0>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x39>;
					};

					dpll_gmac_h12x2_ck@2c4 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x38>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c4>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x14b>;
					};

					dpll_gmac_h13x2_ck@2c8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x38>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2c8>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0xe0>;
					};

					dpll_gmac_m3x2_ck@2bc {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x38>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x2bc>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x14c>;
					};

					gmii_m_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x39>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x14d>;
					};

					hdmi_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x30>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x4f>;
					};

					hdmi_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x30>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x55>;
					};

					l3_iclk_div@100 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						ti,max-div = <0x2>;
						ti,bit-shift = <0x4>;
						reg = <0x100>;
						clocks = <0x1b>;
						ti,index-power-of-two;
						phandle = <0xa>;
					};

					l4_root_clk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0xa>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0xb>;
					};

					video1_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x3a>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x4d>;
					};

					video1_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x3a>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x53>;
					};

					video2_clk2_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x3b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x4e>;
					};

					video2_div_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x3b>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x54>;
					};

					ipu1_gfclk_mux@520 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x16 0x3c>;
						ti,bit-shift = <0x18>;
						reg = <0x520>;
						assigned-clocks = <0x3d>;
						assigned-clock-parents = <0x3c>;
						phandle = <0x3d>;
					};

					mcasp1_ahclkr_mux@550 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x1c>;
						reg = <0x550>;
						phandle = <0xf8>;
					};

					mcasp1_ahclkx_mux@550 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x550>;
						phandle = <0xf7>;
					};

					mcasp1_aux_gfclk_mux@550 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x550>;
						phandle = <0xf6>;
					};

					timer5_gfclk_mux@558 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
						ti,bit-shift = <0x18>;
						reg = <0x558>;
						phandle = <0x14e>;
					};

					timer6_gfclk_mux@560 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
						ti,bit-shift = <0x18>;
						reg = <0x560>;
						phandle = <0x14f>;
					};

					timer7_gfclk_mux@568 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
						ti,bit-shift = <0x18>;
						reg = <0x568>;
						phandle = <0x150>;
					};

					timer8_gfclk_mux@570 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55 0x56>;
						ti,bit-shift = <0x18>;
						reg = <0x570>;
						phandle = <0x151>;
					};

					uart6_gfclk_mux@580 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x580>;
						phandle = <0x152>;
					};

					dummy_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-clock";
						clock-frequency = <0x0>;
						phandle = <0x153>;
					};
				};

				clockdomains {
					phandle = <0x154>;
				};
			};

			cm_core@8000 {
				compatible = "ti,dra7-cm-core";
				reg = <0x8000 0x3000>;
				phandle = <0x155>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					phandle = <0x156>;

					dpll_pcie_ref_ck@200 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x11>;
						reg = <0x200 0x204 0x20c 0x208>;
						phandle = <0x59>;
					};

					dpll_pcie_ref_m2ldo_ck@210 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x59>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x210>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x5a>;
					};

					apll_pcie_in_clk_mux@4ae06118 {
						compatible = "ti,mux-clock";
						clocks = <0x5a 0x5b>;
						#clock-cells = <0x0>;
						reg = <0x21c 0x4>;
						ti,bit-shift = <0x7>;
						phandle = <0x5c>;
					};

					apll_pcie_ck@21c {
						#clock-cells = <0x0>;
						compatible = "ti,dra7-apll-clock";
						clocks = <0x5c 0x59>;
						reg = <0x21c 0x220>;
						phandle = <0x5d>;
					};

					optfclk_pciephy1_32khz@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0x8>;
						phandle = <0xe4>;
					};

					optfclk_pciephy2_32khz@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0x8>;
						phandle = <0xe7>;
					};

					optfclk_pciephy_div@4a00821c {
						compatible = "ti,divider-clock";
						clocks = <0x5d>;
						#clock-cells = <0x0>;
						reg = <0x21c>;
						ti,dividers = <0x2 0x1>;
						ti,bit-shift = <0x8>;
						ti,max-div = <0x2>;
						phandle = <0x5e>;
					};

					optfclk_pciephy1_clk@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x5d>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0x9>;
						phandle = <0xe5>;
					};

					optfclk_pciephy2_clk@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x5d>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0x9>;
						phandle = <0xe8>;
					};

					optfclk_pciephy1_div_clk@4a0093b0 {
						compatible = "ti,gate-clock";
						clocks = <0x5e>;
						#clock-cells = <0x0>;
						reg = <0x13b0>;
						ti,bit-shift = <0xa>;
						phandle = <0xe6>;
					};

					optfclk_pciephy2_div_clk@4a0093b8 {
						compatible = "ti,gate-clock";
						clocks = <0x5e>;
						#clock-cells = <0x0>;
						reg = <0x13b8>;
						ti,bit-shift = <0xa>;
						phandle = <0xe9>;
					};

					apll_pcie_clkvcoldo {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5d>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x157>;
					};

					apll_pcie_clkvcoldo_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5d>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x158>;
					};

					apll_pcie_m2_ck {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x5d>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x91>;
					};

					dpll_per_byp_mux@14c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x5f>;
						ti,bit-shift = <0x17>;
						reg = <0x14c>;
						phandle = <0x60>;
					};

					dpll_per_ck@140 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-clock";
						clocks = <0x11 0x60>;
						reg = <0x140 0x144 0x14c 0x148>;
						phandle = <0x61>;
					};

					dpll_per_m2_ck@150 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x61>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x150>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x62>;
					};

					func_96m_aon_dclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x62>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x9f>;
					};

					dpll_usb_byp_mux@18c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x63>;
						ti,bit-shift = <0x17>;
						reg = <0x18c>;
						phandle = <0x64>;
					};

					dpll_usb_ck@180 {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-j-type-clock";
						clocks = <0x11 0x64>;
						reg = <0x180 0x184 0x18c 0x188>;
						phandle = <0x65>;
					};

					dpll_usb_m2_ck@190 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x65>;
						ti,max-div = <0x7f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x190>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x68>;
					};

					dpll_pcie_ref_m2_ck@210 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x59>;
						ti,max-div = <0x7f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x210>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x90>;
					};

					dpll_per_x2_ck {
						#clock-cells = <0x0>;
						compatible = "ti,omap4-dpll-x2-clock";
						clocks = <0x61>;
						phandle = <0x66>;
					};

					dpll_per_h11x2_ck@158 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x158>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x67>;
					};

					dpll_per_h12x2_ck@15c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x15c>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x6b>;
					};

					dpll_per_h13x2_ck@160 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x160>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x7e>;
					};

					dpll_per_h14x2_ck@164 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x3f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x164>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x74>;
					};

					dpll_per_m2x2_ck@150 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x66>;
						ti,max-div = <0x1f>;
						ti,autoidle-shift = <0x8>;
						reg = <0x150>;
						ti,index-starts-at-one;
						ti,invert-autoidle-bit;
						phandle = <0x58>;
					};

					dpll_usb_clkdcoldo {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x65>;
						clock-mult = <0x1>;
						clock-div = <0x1>;
						phandle = <0x6a>;
					};

					func_128m_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x67>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x79>;
					};

					func_12m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x58>;
						clock-mult = <0x1>;
						clock-div = <0x10>;
						phandle = <0x159>;
					};

					func_24m_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x62>;
						clock-mult = <0x1>;
						clock-div = <0x4>;
						phandle = <0x40>;
					};

					func_48m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x58>;
						clock-mult = <0x1>;
						clock-div = <0x4>;
						phandle = <0x57>;
					};

					func_96m_fclk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x58>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x15a>;
					};

					l3init_60m_fclk@104 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x68>;
						reg = <0x104>;
						ti,dividers = <0x1 0x8>;
						phandle = <0x15b>;
					};

					clkout2_clk@6b0 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x69>;
						ti,bit-shift = <0x8>;
						reg = <0x6b0>;
						phandle = <0x130>;
					};

					l3init_960m_gfclk@6c0 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6a>;
						ti,bit-shift = <0x8>;
						reg = <0x6c0>;
						phandle = <0x6f>;
					};

					dss_32khz_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0xb>;
						reg = <0x1120>;
						phandle = <0x15c>;
					};

					dss_48mhz_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x57>;
						ti,bit-shift = <0x9>;
						reg = <0x1120>;
						phandle = <0x111>;
					};

					dss_dss_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6b>;
						ti,bit-shift = <0x8>;
						reg = <0x1120>;
						ti,set-rate-parent;
						phandle = <0x10d>;
					};

					dss_hdmi_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6c>;
						ti,bit-shift = <0xa>;
						reg = <0x1120>;
						phandle = <0x112>;
					};

					dss_video1_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6d>;
						ti,bit-shift = <0xc>;
						reg = <0x1120>;
						phandle = <0x10e>;
					};

					dss_video2_clk@1120 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6e>;
						ti,bit-shift = <0xd>;
						reg = <0x1120>;
						phandle = <0x10f>;
					};

					gpio2_dbclk@1760 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1760>;
						phandle = <0x15d>;
					};

					gpio3_dbclk@1768 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1768>;
						phandle = <0x15e>;
					};

					gpio4_dbclk@1770 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1770>;
						phandle = <0x15f>;
					};

					gpio5_dbclk@1778 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1778>;
						phandle = <0x160>;
					};

					gpio6_dbclk@1780 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1780>;
						phandle = <0x161>;
					};

					gpio7_dbclk@1810 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1810>;
						phandle = <0x162>;
					};

					gpio8_dbclk@1818 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1818>;
						phandle = <0x163>;
					};

					mmc1_clk32k@1328 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1328>;
						phandle = <0x164>;
					};

					mmc2_clk32k@1330 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1330>;
						phandle = <0x165>;
					};

					mmc3_clk32k@1820 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1820>;
						phandle = <0x166>;
					};

					mmc4_clk32k@1828 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1828>;
						phandle = <0x167>;
					};

					sata_ref_clk@1388 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x11>;
						ti,bit-shift = <0x8>;
						reg = <0x1388>;
						phandle = <0xe3>;
					};

					usb_otg_ss1_refclk960m@13f0 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6f>;
						ti,bit-shift = <0x8>;
						reg = <0x13f0>;
						phandle = <0xec>;
					};

					usb_otg_ss2_refclk960m@1340 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x6f>;
						ti,bit-shift = <0x8>;
						reg = <0x1340>;
						phandle = <0xef>;
					};

					usb_phy1_always_on_clk32k@640 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x640>;
						phandle = <0xeb>;
					};

					usb_phy2_always_on_clk32k@688 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x688>;
						phandle = <0xee>;
					};

					usb_phy3_always_on_clk32k@698 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x698>;
						phandle = <0xf0>;
					};

					atl_dpll_clk_mux@c00 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x51 0x3a 0x3b 0x30>;
						ti,bit-shift = <0x18>;
						reg = <0xc00>;
						phandle = <0x71>;
					};

					atl_gfclk_mux@c00 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xa 0x70 0x71>;
						ti,bit-shift = <0x1a>;
						reg = <0xc00>;
						phandle = <0x10>;
					};

					rmii_50mhz_clk_mux@13d0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x39 0x72>;
						ti,bit-shift = <0x18>;
						reg = <0x13d0>;
						phandle = <0x168>;
					};

					gmac_rft_clk_mux@13d0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3a 0x3b 0x70 0x30 0xa>;
						ti,bit-shift = <0x19>;
						reg = <0x13d0>;
						phandle = <0x108>;
					};

					gpu_core_gclk_mux@1220 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x73 0x74 0x28>;
						ti,bit-shift = <0x18>;
						reg = <0x1220>;
						assigned-clocks = <0x75>;
						assigned-clock-parents = <0x28>;
						phandle = <0x75>;
					};

					gpu_hyd_gclk_mux@1220 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x73 0x74 0x28>;
						ti,bit-shift = <0x1a>;
						reg = <0x1220>;
						assigned-clocks = <0x76>;
						assigned-clock-parents = <0x28>;
						phandle = <0x76>;
					};

					l3instr_ts_gclk_div@e50 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x77>;
						ti,bit-shift = <0x18>;
						reg = <0xe50>;
						ti,dividers = <0x8 0x10 0x20>;
						phandle = <0x169>;
					};

					mcasp2_ahclkr_mux@1860 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x1c>;
						reg = <0x1860>;
						phandle = <0xfb>;
					};

					mcasp2_ahclkx_mux@1860 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1860>;
						phandle = <0xfa>;
					};

					mcasp2_aux_gfclk_mux@1860 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1860>;
						phandle = <0xf9>;
					};

					mcasp3_ahclkx_mux@1868 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1868>;
						assigned-clocks = <0x78>;
						assigned-clock-parents = <0x3e>;
						phandle = <0x78>;
					};

					mcasp3_aux_gfclk_mux@1868 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1868>;
						phandle = <0xfc>;
					};

					mcasp4_ahclkx_mux@1898 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1898>;
						phandle = <0xfe>;
					};

					mcasp4_aux_gfclk_mux@1898 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1898>;
						phandle = <0xfd>;
					};

					mcasp5_ahclkx_mux@1878 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1878>;
						phandle = <0x100>;
					};

					mcasp5_aux_gfclk_mux@1878 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1878>;
						phandle = <0xff>;
					};

					mcasp6_ahclkx_mux@1904 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1904>;
						phandle = <0x102>;
					};

					mcasp6_aux_gfclk_mux@1904 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1904>;
						phandle = <0x101>;
					};

					mcasp7_ahclkx_mux@1908 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x18>;
						reg = <0x1908>;
						phandle = <0x104>;
					};

					mcasp7_aux_gfclk_mux@1908 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x16>;
						reg = <0x1908>;
						phandle = <0x103>;
					};

					mcasp8_ahclkx_mux@1890 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b>;
						ti,bit-shift = <0x16>;
						reg = <0x1890>;
						phandle = <0x106>;
					};

					mcasp8_aux_gfclk_mux@1890 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x4c 0x4d 0x4e 0x4f>;
						ti,bit-shift = <0x18>;
						reg = <0x1890>;
						phandle = <0x105>;
					};

					mmc1_fclk_mux@1328 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x79 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1328>;
						phandle = <0x7a>;
					};

					mmc1_fclk_div@1328 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7a>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1328>;
						ti,index-power-of-two;
						phandle = <0x16a>;
					};

					mmc2_fclk_mux@1330 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x79 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1330>;
						phandle = <0x7b>;
					};

					mmc2_fclk_div@1330 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7b>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1330>;
						ti,index-power-of-two;
						phandle = <0x16b>;
					};

					mmc3_gfclk_mux@1820 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1820>;
						phandle = <0x7c>;
					};

					mmc3_gfclk_div@1820 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7c>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1820>;
						ti,index-power-of-two;
						phandle = <0x16c>;
					};

					mmc4_gfclk_mux@1828 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1828>;
						phandle = <0x7d>;
					};

					mmc4_gfclk_div@1828 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7d>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1828>;
						ti,index-power-of-two;
						phandle = <0x16d>;
					};

					qspi_gfclk_mux@1838 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x79 0x7e>;
						ti,bit-shift = <0x18>;
						reg = <0x1838>;
						phandle = <0x7f>;
					};

					qspi_gfclk_div@1838 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x7f>;
						ti,bit-shift = <0x19>;
						ti,max-div = <0x4>;
						reg = <0x1838>;
						ti,index-power-of-two;
						phandle = <0xe2>;
					};

					timer10_gfclk_mux@1728 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1728>;
						phandle = <0x16e>;
					};

					timer11_gfclk_mux@1730 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1730>;
						phandle = <0x16f>;
					};

					timer13_gfclk_mux@17c8 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x17c8>;
						phandle = <0x170>;
					};

					timer14_gfclk_mux@17d0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x17d0>;
						phandle = <0x171>;
					};

					timer15_gfclk_mux@17d8 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x17d8>;
						phandle = <0x172>;
					};

					timer16_gfclk_mux@1830 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1830>;
						assigned-clocks = <0x80>;
						assigned-clock-parents = <0x52>;
						phandle = <0x80>;
					};

					timer2_gfclk_mux@1738 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1738>;
						phandle = <0x173>;
					};

					timer3_gfclk_mux@1740 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1740>;
						phandle = <0x174>;
					};

					timer4_gfclk_mux@1748 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1748>;
						phandle = <0x175>;
					};

					timer9_gfclk_mux@1750 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1750>;
						phandle = <0x176>;
					};

					uart1_gfclk_mux@1840 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1840>;
						phandle = <0x177>;
					};

					uart2_gfclk_mux@1848 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1848>;
						phandle = <0x178>;
					};

					uart3_gfclk_mux@1850 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1850>;
						phandle = <0x179>;
					};

					uart4_gfclk_mux@1858 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1858>;
						phandle = <0x17a>;
					};

					uart5_gfclk_mux@1870 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1870>;
						phandle = <0x17b>;
					};

					uart7_gfclk_mux@18d0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x18d0>;
						phandle = <0x17c>;
					};

					uart8_gfclk_mux@18e0 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x18e0>;
						phandle = <0x17d>;
					};

					uart9_gfclk_mux@18e8 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x18e8>;
						phandle = <0x17e>;
					};

					vip1_gclk_mux@1020 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xa 0x81>;
						ti,bit-shift = <0x18>;
						reg = <0x1020>;
						phandle = <0x17f>;
					};

					vip2_gclk_mux@1028 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xa 0x81>;
						ti,bit-shift = <0x18>;
						reg = <0x1028>;
						phandle = <0x180>;
					};

					vip3_gclk_mux@1030 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0xa 0x81>;
						ti,bit-shift = <0x18>;
						reg = <0x1030>;
						phandle = <0x181>;
					};
				};

				clockdomains {
					phandle = <0x182>;

					coreaon_clkdm {
						compatible = "ti,clockdomain";
						clocks = <0x65>;
						phandle = <0x183>;
					};
				};
			};
		};

		l4@4ae00000 {
			compatible = "ti,dra7-l4-wkup", "simple-bus";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4ae00000 0x3f000>;
			phandle = <0x184>;

			counter@4000 {
				compatible = "ti,omap-counter32k";
				reg = <0x4000 0x40>;
				ti,hwmods = "counter_32k";
				phandle = <0x185>;
			};

			prm@6000 {
				compatible = "ti,dra7-prm";
				reg = <0x6000 0x3000>;
				interrupts = <0x0 0x6 0x4>;
				phandle = <0x186>;

				clocks {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					phandle = <0x187>;

					sys_clkin1@110 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x82 0x83 0x84 0x85 0x86 0x87 0x88>;
						reg = <0x110>;
						ti,index-starts-at-one;
						phandle = <0x11>;
					};

					abe_dpll_sys_clk_mux@118 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						reg = <0x118>;
						phandle = <0x89>;
					};

					abe_dpll_bypass_clk_mux@114 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x89 0x51>;
						reg = <0x114>;
						phandle = <0x13>;
					};

					abe_dpll_clk_mux@10c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x89 0x51>;
						reg = <0x10c>;
						phandle = <0x12>;
					};

					abe_24m_fclk@11c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x16>;
						reg = <0x11c>;
						ti,dividers = <0x8 0x10>;
						phandle = <0x3e>;
					};

					aess_fclk@178 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8a>;
						reg = <0x178>;
						ti,max-div = <0x2>;
						phandle = <0x8b>;
					};

					abe_giclk_div@174 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8b>;
						reg = <0x174>;
						ti,max-div = <0x2>;
						phandle = <0x52>;
					};

					abe_lp_clk_div@1d8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x16>;
						reg = <0x1d8>;
						ti,dividers = <0x10 0x20>;
						phandle = <0xaa>;
					};

					abe_sys_clk_div@120 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						reg = <0x120>;
						ti,max-div = <0x2>;
						phandle = <0x3f>;
					};

					adc_gfclk_mux@1dc {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45 0x51>;
						reg = <0x1dc>;
						phandle = <0x188>;
					};

					sys_clk1_dclk_div@1c8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						ti,max-div = <0x40>;
						reg = <0x1c8>;
						ti,index-power-of-two;
						phandle = <0x93>;
					};

					sys_clk2_dclk_div@1cc {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x45>;
						ti,max-div = <0x40>;
						reg = <0x1cc>;
						ti,index-power-of-two;
						phandle = <0x94>;
					};

					per_abe_x1_dclk_div@1bc {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x70>;
						ti,max-div = <0x40>;
						reg = <0x1bc>;
						ti,index-power-of-two;
						phandle = <0x95>;
					};

					dsp_gclk_div@18c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x21>;
						ti,max-div = <0x40>;
						reg = <0x18c>;
						ti,index-power-of-two;
						phandle = <0x97>;
					};

					gpu_dclk@1a0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x28>;
						ti,max-div = <0x40>;
						reg = <0x1a0>;
						ti,index-power-of-two;
						phandle = <0x99>;
					};

					emif_phy_dclk_div@190 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8c>;
						ti,max-div = <0x40>;
						reg = <0x190>;
						ti,index-power-of-two;
						phandle = <0x9b>;
					};

					gmac_250m_dclk_div@19c {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8d>;
						ti,max-div = <0x40>;
						reg = <0x19c>;
						ti,index-power-of-two;
						phandle = <0x8e>;
					};

					gmac_main_clk {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x8e>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x107>;
					};

					l3init_480m_dclk_div@1ac {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x68>;
						ti,max-div = <0x40>;
						reg = <0x1ac>;
						ti,index-power-of-two;
						phandle = <0xa0>;
					};

					usb_otg_dclk_div@184 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x8f>;
						ti,max-div = <0x40>;
						reg = <0x184>;
						ti,index-power-of-two;
						phandle = <0xa1>;
					};

					sata_dclk_div@1c0 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						ti,max-div = <0x40>;
						reg = <0x1c0>;
						ti,index-power-of-two;
						phandle = <0xa2>;
					};

					pcie2_dclk_div@1b8 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x90>;
						ti,max-div = <0x40>;
						reg = <0x1b8>;
						ti,index-power-of-two;
						phandle = <0xa3>;
					};

					pcie_dclk_div@1b4 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x91>;
						ti,max-div = <0x40>;
						reg = <0x1b4>;
						ti,index-power-of-two;
						phandle = <0xa4>;
					};

					emu_dclk_div@194 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						ti,max-div = <0x40>;
						reg = <0x194>;
						ti,index-power-of-two;
						phandle = <0xa5>;
					};

					secure_32k_dclk_div@1c4 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x92>;
						ti,max-div = <0x40>;
						reg = <0x1c4>;
						ti,index-power-of-two;
						phandle = <0xa6>;
					};

					clkoutmux0_clk_mux@158 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
						reg = <0x158>;
						phandle = <0x56>;
					};

					clkoutmux1_clk_mux@15c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
						reg = <0x15c>;
						phandle = <0x189>;
					};

					clkoutmux2_clk_mux@160 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x8e 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7>;
						reg = <0x160>;
						phandle = <0x69>;
					};

					custefuse_sys_gfclk_div {
						#clock-cells = <0x0>;
						compatible = "fixed-factor-clock";
						clocks = <0x11>;
						clock-mult = <0x1>;
						clock-div = <0x2>;
						phandle = <0x18a>;
					};

					eve_clk@180 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x34 0x37>;
						reg = <0x180>;
						phandle = <0x18b>;
					};

					hdmi_dpll_clk_mux@164 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						reg = <0x164>;
						phandle = <0x6c>;
					};

					mlb_clk@134 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xa8>;
						ti,max-div = <0x40>;
						reg = <0x134>;
						ti,index-power-of-two;
						phandle = <0x4a>;
					};

					mlbp_clk@130 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0xa9>;
						ti,max-div = <0x40>;
						reg = <0x130>;
						ti,index-power-of-two;
						phandle = <0x4b>;
					};

					per_abe_x1_gfclk2_div@138 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x70>;
						ti,max-div = <0x40>;
						reg = <0x138>;
						ti,index-power-of-two;
						phandle = <0x4c>;
					};

					timer_sys_clk_div@144 {
						#clock-cells = <0x0>;
						compatible = "ti,divider-clock";
						clocks = <0x11>;
						reg = <0x144>;
						ti,max-div = <0x2>;
						phandle = <0x50>;
					};

					video1_dpll_clk_mux@168 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						reg = <0x168>;
						phandle = <0x6d>;
					};

					video2_dpll_clk_mux@16c {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						reg = <0x16c>;
						phandle = <0x6e>;
					};

					wkupaon_iclk_mux@108 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0xaa>;
						reg = <0x108>;
						phandle = <0x77>;
					};

					gpio1_dbclk@1838 {
						#clock-cells = <0x0>;
						compatible = "ti,gate-clock";
						clocks = <0x51>;
						ti,bit-shift = <0x8>;
						reg = <0x1838>;
						phandle = <0x18c>;
					};

					dcan1_sys_clk_mux@1888 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x11 0x45>;
						ti,bit-shift = <0x18>;
						reg = <0x1888>;
						phandle = <0x10b>;
					};

					timer1_gfclk_mux@1840 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x50 0x51 0x45 0x46 0x47 0x48 0x49 0x52 0x53 0x54 0x55>;
						ti,bit-shift = <0x18>;
						reg = <0x1840>;
						phandle = <0x18d>;
					};

					uart10_gfclk_mux@1880 {
						#clock-cells = <0x0>;
						compatible = "ti,mux-clock";
						clocks = <0x57 0x58>;
						ti,bit-shift = <0x18>;
						reg = <0x1880>;
						phandle = <0x18e>;
					};
				};

				clockdomains {
					phandle = <0x18f>;
				};
			};

			scm_conf@c000 {
				compatible = "syscon";
				reg = <0xc000 0x1000>;
				phandle = <0x7>;
			};
		};

		axi@0 {
			compatible = "simple-bus";
			#size-cells = <0x1>;
			#address-cells = <0x1>;
			ranges = <0x51000000 0x51000000 0x3000 0x0 0x20000000 0x10000000>;

			pcie@51000000 {
				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
				reg = <0x51000000 0x2000 0x51002000 0x14c 0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0x0 0xe8 0x4 0x0 0xe9 0x4>;
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				device_type = "pci";
				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x20013000 0x13000 0x0 0xffed000>;
				bus-range = <0x0 0xff>;
				#interrupt-cells = <0x1>;
				num-lanes = <0x1>;
				linux,pci-domain = <0x0>;
				ti,hwmods = "pcie1";
				phys = <0xab>;
				phy-names = "pcie-phy0";
				ti,syscon-conf = <0x9>;
				ti,syscon-pcie = <0xac>;
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0xad 0x1 0x0 0x0 0x0 0x2 0xad 0x2 0x0 0x0 0x0 0x3 0xad 0x3 0x0 0x0 0x0 0x4 0xad 0x4>;
				ti,syscon-unaligned-access = <0xae 0x14 0x1>;
				status = "ok";
				gpios = <0xaf 0x8 0x1>;
				phandle = <0x190>;

				interrupt-controller {
					interrupt-controller;
					#address-cells = <0x0>;
					#interrupt-cells = <0x1>;
					phandle = <0xad>;
				};
			};

			pcie_ep@51000000 {
				compatible = "ti,dra746-pcie-ep", "ti,dra7-pcie-ep";
				reg = <0x51000000 0x28 0x51002000 0x14c 0x51001000 0x28 0x1000 0x10000000>;
				reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
				interrupts = <0x0 0xe8 0x4>;
				num-lanes = <0x1>;
				num-ib-windows = <0x4>;
				num-ob-windows = <0x10>;
				ti,hwmods = "pcie1";
				phys = <0xab>;
				phy-names = "pcie-phy0";
				ti,syscon-unaligned-access = <0xae 0x14 0x1>;
				ti,syscon-conf = <0x9>;
				ti,syscon-pcie = <0xac>;
				status = "disabled";
				gpios = <0xaf 0x8 0x1>;
				phandle = <0x191>;
			};
		};

		axi@1 {
			compatible = "simple-bus";
			#size-cells = <0x1>;
			#address-cells = <0x1>;
			ranges = <0x51800000 0x51800000 0x3000 0x0 0x30000000 0x10000000>;
			status = "disabled";

			pcie@51800000 {
				compatible = "ti,dra746-pcie-rc", "ti,dra7-pcie";
				reg = <0x51800000 0x2000 0x51802000 0x14c 0x1000 0x2000>;
				reg-names = "rc_dbics", "ti_conf", "config";
				interrupts = <0x0 0x163 0x4 0x0 0x164 0x4>;
				#address-cells = <0x3>;
				#size-cells = <0x2>;
				device_type = "pci";
				ranges = <0x81000000 0x0 0x0 0x3000 0x0 0x10000 0x82000000 0x0 0x30013000 0x13000 0x0 0xffed000>;
				bus-range = <0x0 0xff>;
				#interrupt-cells = <0x1>;
				num-lanes = <0x1>;
				linux,pci-domain = <0x1>;
				ti,hwmods = "pcie2";
				phys = <0xb0>;
				phy-names = "pcie-phy0";
				interrupt-map-mask = <0x0 0x0 0x0 0x7>;
				interrupt-map = <0x0 0x0 0x0 0x1 0xb1 0x1 0x0 0x0 0x0 0x2 0xb1 0x2 0x0 0x0 0x0 0x3 0xb1 0x3 0x0 0x0 0x0 0x4 0xb1 0x4>;
				ti,syscon-unaligned-access = <0xae 0x14 0x2>;
				phandle = <0x192>;

				interrupt-controller {
					interrupt-controller;
					#address-cells = <0x0>;
					#interrupt-cells = <0x1>;
					phandle = <0xb1>;
				};
			};
		};

		ocmcram@40300000 {
			compatible = "mmio-sram";
			reg = <0x40300000 0x80000>;
			ranges = <0x0 0x40300000 0x80000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			phandle = <0x193>;

			sram-hs@0 {
				compatible = "ti,secure-ram";
				reg = <0x0 0x0>;
			};
		};

		ocmcram@40400000 {
			status = "disabled";
			compatible = "mmio-sram";
			reg = <0x40400000 0x100000>;
			ranges = <0x0 0x40400000 0x100000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			phandle = <0x194>;
		};

		ocmcram@40500000 {
			status = "disabled";
			compatible = "mmio-sram";
			reg = <0x40500000 0x100000>;
			ranges = <0x0 0x40500000 0x100000>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			phandle = <0x195>;
		};

		bandgap@4a0021e0 {
			reg = <0x4a0021e0 0xc 0x4a00232c 0xc 0x4a002380 0x2c 0x4a0023c0 0x3c 0x4a002564 0x8 0x4a002574 0x50>;
			compatible = "ti,dra752-bandgap";
			interrupts = <0x0 0x79 0x4>;
			#thermal-sensor-cells = <0x1>;
			phandle = <0x11f>;
		};

		dsp_system@40d00000 {
			compatible = "syscon";
			reg = <0x40d00000 0x100>;
			phandle = <0xde>;
		};

		padconf@4844a000 {
			compatible = "ti,dra7-iodelay";
			reg = <0x4844a000 0xd1c>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			#pinctrl-cells = <0x2>;
			phandle = <0x196>;

			mmc1_iodelay_ddr_rev11_conf {
				pinctrl-pin-array = <0x618 0x23c 0x21c 0x620 0x5f5 0x0 0x624 0x0 0x258 0x628 0x0 0x0 0x62c 0x37 0x0 0x630 0x193 0x78 0x634 0x0 0x0 0x638 0x0 0x0 0x63c 0x17 0x3c 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x19 0x3c 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
				phandle = <0x197>;
			};

			mmc1_iodelay_ddr50_rev20_conf {
				pinctrl-pin-array = <0x618 0x434 0x14a 0x620 0x4f7 0x0 0x624 0x2d2 0x0 0x628 0x0 0x0 0x62c 0x0 0x0 0x630 0x2ef 0x0 0x634 0x0 0x0 0x638 0x14 0x0 0x63c 0x100 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x648 0x107 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x654 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
				phandle = <0xd8>;
			};

			mmc1_iodelay_sdr104_rev11_conf {
				pinctrl-pin-array = <0x620 0x427 0x11 0x628 0x0 0x0 0x62c 0x17 0x0 0x634 0x0 0x0 0x638 0x0 0x0 0x640 0x0 0x0 0x644 0x2 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
				phandle = <0x198>;
			};

			mmc1_iodelay_sdr104_rev20_conf {
				pinctrl-pin-array = <0x620 0x258 0x190 0x628 0x0 0x0 0x62c 0x0 0x0 0x634 0x0 0x0 0x638 0x1e 0x0 0x640 0x0 0x0 0x644 0x0 0x0 0x64c 0x0 0x0 0x650 0x0 0x0 0x658 0x0 0x0 0x65c 0x0 0x0>;
				phandle = <0xda>;
			};

			mmc2_iodelay_hs200_rev11_conf {
				pinctrl-pin-array = <0x190 0x26d 0x258 0x194 0x12c 0x0 0x1a8 0x2e3 0x258 0x1ac 0xf0 0x0 0x1b4 0x32c 0x258 0x1b8 0xf0 0x0 0x1c0 0x3ba 0x258 0x1c4 0x3c 0x0 0x1d0 0x53c 0x1a4 0x1d8 0x3a7 0x258 0x1dc 0x0 0x0 0x1e4 0x20d 0x258 0x1e8 0x78 0x0 0x1f0 0x2ff 0x258 0x1f4 0xe1 0x0 0x1fc 0x235 0x258 0x200 0x3c 0x0 0x364 0x3c9 0x258 0x368 0xb4 0x0>;
				phandle = <0x199>;
			};

			mmc2_iodelay_hs200_rev20_conf {
				pinctrl-pin-array = <0x190 0x112 0x0 0x194 0xa2 0x0 0x1a8 0x191 0x0 0x1ac 0x49 0x0 0x1b4 0x1d1 0x0 0x1b8 0x73 0x0 0x1c0 0x279 0x0 0x1c4 0x2f 0x0 0x1d0 0x3a7 0x118 0x1d8 0x26d 0x0 0x1dc 0x0 0x0 0x1e4 0xb7 0x0 0x1e8 0x0 0x0 0x1f0 0x1d3 0x0 0x1f4 0x0 0x0 0x1fc 0x106 0x0 0x200 0x2e 0x0 0x364 0x2ac 0x0 0x368 0x4c 0x0>;
				phandle = <0x19a>;
			};

			mmc2_iodelay_ddr_3_3v_rev11_conf {
				pinctrl-pin-array = <0x18c 0x0 0x78 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x109 0x168 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x78 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x78 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x11f 0x1a4 0x1d0 0x36f 0x0 0x1d4 0x90 0xf0 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x78 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x78 0xb4 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
				phandle = <0x19b>;
			};

			mmc2_iodelay_ddr_1_8v_rev11_conf {
				pinctrl-pin-array = <0x18c 0x0 0x0 0x190 0x0 0x0 0x194 0xae 0x0 0x1a4 0x112 0xf0 0x1a8 0x0 0x0 0x1ac 0xa8 0x0 0x1b0 0x0 0x3c 0x1b4 0x0 0x0 0x1b8 0x88 0x0 0x1bc 0x0 0x3c 0x1c0 0x0 0x0 0x1c4 0x0 0x0 0x1c8 0x202 0x168 0x1d0 0x36f 0x0 0x1d4 0xbb 0x78 0x1d8 0x0 0x0 0x1dc 0x0 0x0 0x1e0 0x0 0x0 0x1e4 0x0 0x0 0x1e8 0x22 0x0 0x1ec 0x0 0x3c 0x1f0 0x0 0x0 0x1f4 0x78 0x0 0x1f8 0x79 0x3c 0x1fc 0x0 0x0 0x200 0x0 0x0 0x360 0x0 0x0 0x364 0x0 0x0 0x368 0xb 0x0>;
				phandle = <0x19c>;
			};

			mmc3_iodelay_manual1_conf {
				pinctrl-pin-array = <0x678 0x196 0x0 0x680 0x293 0x0 0x684 0x0 0x0 0x688 0x0 0x0 0x68c 0x0 0x0 0x690 0x82 0x0 0x694 0x0 0x0 0x698 0x0 0x0 0x69c 0xa9 0x0 0x6a0 0x0 0x0 0x6a4 0x0 0x0 0x6a8 0x0 0x0 0x6ac 0x0 0x0 0x6b0 0x0 0x0 0x6b4 0x1c9 0x0 0x6b8 0x0 0x0 0x6bc 0x0 0x0>;
				phandle = <0x19d>;
			};

			mmc4_iodelay_ds_rev11_conf {
				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x60 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x246 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x187 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x231 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x24c 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
				phandle = <0x19e>;
			};

			mmc4_iodelay_ds_rev20_conf {
				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x0 0x0 0x84c 0x133 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x311 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x265 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x2ab 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x343 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
				phandle = <0x19f>;
			};

			mmc4_iodelay_sdr12_hs_sdr25_rev11_conf {
				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0xa5b 0x0 0x84c 0x624 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x779 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x6b9 0x0 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x763 0x0 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x77f 0x0 0x898 0x0 0x0 0x89c 0x0 0x0>;
				phandle = <0x1a0>;
			};

			mmc4_iodelay_sdr12_hs_sdr25_rev20_conf {
				pinctrl-pin-array = <0x840 0x0 0x0 0x848 0x47b 0x0 0x84c 0x72a 0x0 0x850 0x0 0x0 0x854 0x0 0x0 0x870 0x875 0x0 0x874 0x0 0x0 0x878 0x0 0x0 0x87c 0x789 0x40 0x880 0x0 0x0 0x884 0x0 0x0 0x888 0x78f 0x80 0x88c 0x0 0x0 0x890 0x0 0x0 0x894 0x87c 0x2c 0x898 0x0 0x0 0x89c 0x0 0x0>;
				phandle = <0x1a1>;
			};
		};

		dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <0x0 0x7 0x4 0x0 0x8 0x4 0x0 0x9 0x4 0x0 0xa 0x4>;
			#dma-cells = <0x1>;
			dma-channels = <0x20>;
			dma-requests = <0x7f>;
			phandle = <0xe>;
		};

		edma@43300000 {
			compatible = "ti,edma3-tpcc";
			ti,hwmods = "tpcc";
			reg = <0x43300000 0x100000>;
			reg-names = "edma3_cc";
			interrupts = <0x0 0x169 0x4 0x0 0x168 0x4 0x0 0x167 0x4>;
			interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
			dma-requests = <0x40>;
			#dma-cells = <0x2>;
			ti,tptcs = <0xb2 0x7 0xb3 0x0>;
			phandle = <0xf>;
		};

		tptc@43400000 {
			compatible = "ti,edma3-tptc";
			ti,hwmods = "tptc0";
			reg = <0x43400000 0x100000>;
			interrupts = <0x0 0x172 0x4>;
			interrupt-names = "edma3_tcerrint";
			phandle = <0xb2>;
		};

		tptc@43500000 {
			compatible = "ti,edma3-tptc";
			ti,hwmods = "tptc1";
			reg = <0x43500000 0x100000>;
			interrupts = <0x0 0x173 0x4>;
			interrupt-names = "edma3_tcerrint";
			phandle = <0xb3>;
		};

		gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <0x0 0x18 0x4>;
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xcb>;
		};

		gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0x0 0x19 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xaf>;
		};

		gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0x0 0x1a 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x1a2>;
		};

		gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0x0 0x1b 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xcd>;
		};

		gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0x0 0x1c 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x1a3>;
		};

		gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0x0 0x1d 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x1a4>;
		};

		gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <0x0 0x1e 0x4>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			ti,no-reset-on-init;
			ti,no-idle-on-init;
			phandle = <0xce>;
		};

		gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <0x0 0x74 0x4>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x1a5>;
		};

		serial@4806a000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts-extended = <0x1 0x0 0x43 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x31 0xb4 0x32>;
			dma-names = "tx", "rx";
			phandle = <0x1a6>;
		};

		serial@4806c000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0x0 0x44 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x33 0xb4 0x34>;
			dma-names = "tx", "rx";
			phandle = <0x1a7>;
		};

		serial@48020000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0x0 0x45 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <0x2dc6c00>;
			status = "okay";
			dmas = <0xb4 0x35 0xb4 0x36>;
			dma-names = "tx", "rx";
			interrupts-extended = <0x1 0x0 0x45 0x4 0xb5 0x3f8>;
			phandle = <0x1a8>;
		};

		serial@4806e000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0x0 0x41 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x37 0xb4 0x38>;
			dma-names = "tx", "rx";
			phandle = <0x1a9>;
		};

		serial@48066000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0x0 0x64 0x4>;
			ti,hwmods = "uart5";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x3f 0xb4 0x40>;
			dma-names = "tx", "rx";
			phandle = <0x1aa>;
		};

		serial@48068000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0x0 0x65 0x4>;
			ti,hwmods = "uart6";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			dmas = <0xb4 0x4f 0xb4 0x50>;
			dma-names = "tx", "rx";
			phandle = <0x1ab>;
		};

		serial@48420000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48420000 0x100>;
			interrupts = <0x0 0xda 0x4>;
			ti,hwmods = "uart7";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			phandle = <0x1ac>;
		};

		serial@48422000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48422000 0x100>;
			interrupts = <0x0 0xdb 0x4>;
			ti,hwmods = "uart8";
			clock-frequency = <0x2dc6c00>;
			status = "okay";
			phandle = <0x1ad>;
		};

		serial@48424000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x48424000 0x100>;
			interrupts = <0x0 0xdc 0x4>;
			ti,hwmods = "uart9";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			phandle = <0x1ae>;
		};

		serial@4ae2b000 {
			compatible = "ti,dra742-uart", "ti,omap4-uart";
			reg = <0x4ae2b000 0x100>;
			interrupts = <0x0 0xdd 0x4>;
			ti,hwmods = "uart10";
			clock-frequency = <0x2dc6c00>;
			status = "disabled";
			phandle = <0x1af>;
		};

		mailbox@4a0f4000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4a0f4000 0x200>;
			interrupts = <0x0 0x15 0x4 0x0 0x87 0x4 0x0 0x86 0x4>;
			ti,hwmods = "mailbox1";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x3>;
			ti,mbox-num-fifos = <0x8>;
			status = "disabled";
			phandle = <0x1b0>;
		};

		mailbox@4883a000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883a000 0x200>;
			interrupts = <0x0 0xed 0x4 0x0 0xee 0x4 0x0 0xef 0x4 0x0 0xf0 0x4>;
			ti,hwmods = "mailbox2";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b1>;
		};

		mailbox@4883c000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883c000 0x200>;
			interrupts = <0x0 0xf1 0x4 0x0 0xf2 0x4 0x0 0xf3 0x4 0x0 0xf4 0x4>;
			ti,hwmods = "mailbox3";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b2>;
		};

		mailbox@4883e000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4883e000 0x200>;
			interrupts = <0x0 0xf5 0x4 0x0 0xf6 0x4 0x0 0xf7 0x4 0x0 0xf8 0x4>;
			ti,hwmods = "mailbox4";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b3>;
		};

		mailbox@48840000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48840000 0x200>;
			interrupts = <0x0 0xf9 0x4 0x0 0xfa 0x4 0x0 0xfb 0x4 0x0 0xfc 0x4>;
			ti,hwmods = "mailbox5";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "okay";
			phandle = <0xb7>;

			mbox_ipu1_ipc3x {
				ti,mbox-tx = <0x6 0x2 0x2>;
				ti,mbox-rx = <0x4 0x2 0x2>;
				status = "okay";
				phandle = <0xb8>;
			};

			mbox_dsp1_ipc3x {
				ti,mbox-tx = <0x5 0x2 0x2>;
				ti,mbox-rx = <0x1 0x2 0x2>;
				status = "okay";
				phandle = <0xc7>;
			};
		};

		mailbox@48842000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48842000 0x200>;
			interrupts = <0x0 0xfd 0x4 0x0 0xfe 0x4 0x0 0xff 0x4 0x0 0x100 0x4>;
			ti,hwmods = "mailbox6";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "okay";
			phandle = <0xbf>;

			mbox_ipu2_ipc3x {
				ti,mbox-tx = <0x6 0x2 0x2>;
				ti,mbox-rx = <0x4 0x2 0x2>;
				status = "okay";
				phandle = <0xc0>;
			};

			mbox_dsp2_ipc3x {
				ti,mbox-tx = <0x5 0x2 0x2>;
				ti,mbox-rx = <0x1 0x2 0x2>;
				status = "okay";
				phandle = <0x11b>;
			};
		};

		mailbox@48844000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48844000 0x200>;
			interrupts = <0x0 0x101 0x4 0x0 0x102 0x4 0x0 0x103 0x4 0x0 0x104 0x4>;
			ti,hwmods = "mailbox7";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b4>;
		};

		mailbox@48846000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48846000 0x200>;
			interrupts = <0x0 0x105 0x4 0x0 0x106 0x4 0x0 0x107 0x4 0x0 0x108 0x4>;
			ti,hwmods = "mailbox8";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b5>;
		};

		mailbox@4885e000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x4885e000 0x200>;
			interrupts = <0x0 0x109 0x4 0x0 0x10a 0x4 0x0 0x10b 0x4 0x0 0x10c 0x4>;
			ti,hwmods = "mailbox9";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b6>;
		};

		mailbox@48860000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48860000 0x200>;
			interrupts = <0x0 0x10d 0x4 0x0 0x10e 0x4 0x0 0x10f 0x4 0x0 0x110 0x4>;
			ti,hwmods = "mailbox10";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b7>;
		};

		mailbox@48862000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48862000 0x200>;
			interrupts = <0x0 0x111 0x4 0x0 0x112 0x4 0x0 0x113 0x4 0x0 0x114 0x4>;
			ti,hwmods = "mailbox11";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b8>;
		};

		mailbox@48864000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48864000 0x200>;
			interrupts = <0x0 0x115 0x4 0x0 0x116 0x4 0x0 0x117 0x4 0x0 0x118 0x4>;
			ti,hwmods = "mailbox12";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1b9>;
		};

		mailbox@48802000 {
			compatible = "ti,omap4-mailbox";
			reg = <0x48802000 0x200>;
			interrupts = <0x0 0x17b 0x4 0x0 0x17c 0x4 0x0 0x17d 0x4 0x0 0x17e 0x4>;
			ti,hwmods = "mailbox13";
			#mbox-cells = <0x1>;
			ti,mbox-num-users = <0x4>;
			ti,mbox-num-fifos = <0xc>;
			status = "disabled";
			phandle = <0x1ba>;
		};

		timer@4ae18000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <0x0 0x20 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
			phandle = <0x1bb>;
		};

		timer@48032000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0x0 0x21 0x4>;
			ti,hwmods = "timer2";
			phandle = <0x1bc>;
		};

		timer@48034000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0x0 0x22 0x4>;
			ti,hwmods = "timer3";
			phandle = <0xc1>;
		};

		timer@48036000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0x0 0x23 0x4>;
			ti,hwmods = "timer4";
			phandle = <0xc2>;
		};

		timer@48820000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48820000 0x80>;
			interrupts = <0x0 0x24 0x4>;
			ti,hwmods = "timer5";
			phandle = <0xc8>;
		};

		timer@48822000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48822000 0x80>;
			interrupts = <0x0 0x25 0x4>;
			ti,hwmods = "timer6";
			phandle = <0x11c>;
		};

		timer@48824000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48824000 0x80>;
			interrupts = <0x0 0x26 0x4>;
			ti,hwmods = "timer7";
			phandle = <0xbb>;
		};

		timer@48826000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48826000 0x80>;
			interrupts = <0x0 0x27 0x4>;
			ti,hwmods = "timer8";
			phandle = <0xbc>;
		};

		timer@4803e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0x0 0x28 0x4>;
			ti,hwmods = "timer9";
			phandle = <0xc3>;
		};

		timer@48086000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0x0 0x29 0x4>;
			ti,hwmods = "timer10";
			phandle = <0xc9>;
		};

		timer@48088000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0x0 0x2a 0x4>;
			ti,hwmods = "timer11";
			phandle = <0xb9>;
		};

		timer@4ae20000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae20000 0x80>;
			interrupts = <0x0 0x5a 0x4>;
			ti,hwmods = "timer12";
			ti,timer-alwon;
			ti,timer-secure;
			phandle = <0x1bd>;
		};

		timer@48828000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48828000 0x80>;
			interrupts = <0x0 0x153 0x4>;
			ti,hwmods = "timer13";
			phandle = <0x11d>;
		};

		timer@4882a000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882a000 0x80>;
			interrupts = <0x0 0x154 0x4>;
			ti,hwmods = "timer14";
			phandle = <0xba>;
		};

		timer@4882c000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882c000 0x80>;
			interrupts = <0x0 0x155 0x4>;
			ti,hwmods = "timer15";
			phandle = <0x1be>;
		};

		timer@4882e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4882e000 0x80>;
			interrupts = <0x0 0x156 0x4>;
			ti,hwmods = "timer16";
			phandle = <0x1bf>;
		};

		wdt@4ae14000 {
			compatible = "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <0x0 0x4b 0x4>;
			ti,hwmods = "wd_timer2";
			phandle = <0x1c0>;
		};

		spinlock@4a0f6000 {
			compatible = "ti,omap4-hwspinlock";
			reg = <0x4a0f6000 0x1000>;
			ti,hwmods = "spinlock";
			#hwlock-cells = <0x1>;
			phandle = <0x1c1>;
		};

		dmm@4e000000 {
			compatible = "ti,dra7-dmm", "ti,omap5-dmm";
			reg = <0x4e000000 0x800>;
			interrupts = <0x0 0x6c 0x4>;
			ti,hwmods = "dmm";
		};

		ipu@58820000 {
			compatible = "ti,dra7-ipu";
			reg = <0x58820000 0x10000>;
			reg-names = "l2ram";
			ti,hwmods = "ipu1";
			iommus = <0xb6>;
			ti,rproc-standby-info = <0x4a005520>;
			status = "okay";
			mboxes = <0xb7 0xb8>;
			timers = <0xb9 0xba>;
			watchdog-timers = <0xbb 0xbc>;
			memory-region = <0xbd>;
			phandle = <0x1c2>;
		};

		ipu@55020000 {
			compatible = "ti,dra7-ipu";
			reg = <0x55020000 0x10000>;
			reg-names = "l2ram";
			ti,hwmods = "ipu2";
			iommus = <0xbe>;
			ti,rproc-standby-info = <0x4a008920>;
			status = "okay";
			mboxes = <0xbf 0xc0>;
			timers = <0xc1>;
			watchdog-timers = <0xc2 0xc3>;
			memory-region = <0xc4>;
			phandle = <0x1c3>;
		};

		dsp@40800000 {
			compatible = "ti,dra7-dsp";
			reg = <0x40800000 0x48000 0x40e00000 0x8000 0x40f00000 0x8000>;
			reg-names = "l2ram", "l1pram", "l1dram";
			ti,hwmods = "dsp1";
			syscon-bootreg = <0x9 0x55c>;
			iommus = <0xc5 0xc6>;
			ti,rproc-standby-info = <0x4a005420>;
			status = "okay";
			mboxes = <0xb7 0xc7>;
			timers = <0xc8>;
			watchdog-timers = <0xc9>;
			memory-region = <0xca>;
			phandle = <0x1c4>;
		};

		i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0x0 0x33 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c1";
			status = "okay";
			clock-frequency = <0x61a80>;
			phandle = <0x1c5>;

			tps659038@58 {
				status = "disabled";
				compatible = "ti,tps659038";
				reg = <0x58>;
				interrupt-parent = <0xcb>;
				interrupts = <0x0 0x8>;
				#interrupt-cells = <0x2>;
				interrupt-controller;
				ti,system-power-controller;
				ti,palmas-override-powerhold;
				phandle = <0xcc>;

				tps659038_pmic {
					compatible = "ti,tps659038-pmic";

					regulators {

						smps12 {
							regulator-name = "smps12";
							regulator-min-microvolt = <0xcf850>;
							regulator-max-microvolt = <0x1312d0>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x6>;
						};

						smps3 {
							regulator-name = "smps3";
							regulator-min-microvolt = <0x149970>;
							regulator-max-microvolt = <0x149970>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x128>;
						};

						smps45 {
							regulator-name = "smps45";
							regulator-min-microvolt = <0xcf850>;
							regulator-max-microvolt = <0x1312d0>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1c6>;
						};

						smps6 {
							regulator-name = "smps6";
							regulator-min-microvolt = <0xcf850>;
							regulator-max-microvolt = <0x118c30>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1c7>;
						};

						smps8 {
							regulator-name = "smps8";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x1b7740>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1c8>;
						};

						ldo1 {
							regulator-name = "ldo1";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x325aa0>;
							regulator-boot-on;
							regulator-always-on;
							phandle = <0x1c9>;
						};

						ldo2 {
							regulator-name = "ldo2";
							regulator-min-microvolt = <0x325aa0>;
							regulator-max-microvolt = <0x325aa0>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1ca>;
						};

						ldo3 {
							regulator-name = "ldo3";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x1b7740>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1cb>;
						};

						ldo4 {
							regulator-name = "ldo4";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x1b7740>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x113>;
						};

						ldo9 {
							regulator-name = "ldo9";
							regulator-min-microvolt = <0x100590>;
							regulator-max-microvolt = <0x100590>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x1cc>;
						};

						ldoln {
							regulator-name = "ldoln";
							regulator-min-microvolt = <0x1b7740>;
							regulator-max-microvolt = <0x1b7740>;
							regulator-always-on;
							regulator-boot-on;
							phandle = <0x110>;
						};

						ldousb {
							regulator-name = "ldousb";
							regulator-min-microvolt = <0x325aa0>;
							regulator-max-microvolt = <0x325aa0>;
							regulator-boot-on;
							phandle = <0xed>;
						};

						regen1 {
							regulator-name = "regen1";
							regulator-boot-on;
							regulator-always-on;
							phandle = <0x127>;
						};
					};
				};

				tps659038_rtc {
					compatible = "ti,palmas-rtc";
					interrupt-parent = <0xcc>;
					interrupts = <0x8 0x2>;
					wakeup-source;
					phandle = <0x1cd>;
				};

				tps659038_pwr_button {
					compatible = "ti,palmas-pwrbutton";
					interrupt-parent = <0xcc>;
					interrupts = <0x1 0x2>;
					wakeup-source;
					ti,palmas-long-press-seconds = <0xc>;
					phandle = <0x1ce>;
				};

				tps659038_gpio {
					compatible = "ti,palmas-gpio";
					gpio-controller;
					#gpio-cells = <0x2>;
					phandle = <0x129>;
				};

				tps659038_usb {
					compatible = "ti,palmas-usb-vid";
					ti,enable-vbus-detection;
					vbus-gpio = <0xcd 0x15 0x0>;
					phandle = <0xf3>;
				};
			};

			tmp102@48 {
				compatible = "ti,tmp102";
				reg = <0x48>;
				interrupt-parent = <0xce>;
				interrupts = <0x10 0x8>;
				#thermal-sensor-cells = <0x1>;
				phandle = <0x124>;
			};

			tlv320aic3104@18 {
				#sound-dai-cells = <0x0>;
				compatible = "ti,tlv320aic3104";
				reg = <0x18>;
				assigned-clocks = <0x69>;
				assigned-clock-parents = <0x94>;
				status = "okay";
				adc-settle-ms = <0x28>;
				AVDD-supply = <0xcf>;
				IOVDD-supply = <0xcf>;
				DRVDD-supply = <0xcf>;
				DVDD-supply = <0xd0>;
				phandle = <0x12f>;
			};

			eeprom@50 {
				compatible = "atmel,24c32";
				reg = <0x50>;
				phandle = <0x1cf>;
			};
		};

		i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0x0 0x34 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c2";
			status = "disabled";
			phandle = <0x1d0>;
		};

		i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0x0 0x38 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c3";
			status = "okay";
			clock-frequency = <0x61a80>;
			phandle = <0x1d1>;

			rtc@6f {
				compatible = "microchip,mcp7941x";
				reg = <0x6f>;
				interrupts-extended = <0x1 0x0 0x2 0x1 0xb5 0x424>;
				interrupt-names = "irq", "wakeup";
				vcc-supply = <0xcf>;
				wakeup-source;
				phandle = <0x1d2>;
			};
		};

		i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <0x0 0x39 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c4";
			status = "disabled";
			phandle = <0x1d3>;
		};

		i2c@4807c000 {
			clock-frequency = <0x61a80>;
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <0x0 0x37 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "i2c5";
			status = "okay";
			phandle = <0x1d4>;

			pixcir_ts@5c {
				touchscreen-size-y = <0x258>;
				touchscreen-size-x = <0x400>;
				reset-gpio = <0xaf 0x6 0x0>;
				reg = <0x5c>;
				interrupts = <0x4 0x0>;
				interrupt-parent = <0xaf>;
				attb-gpio = <0xaf 0x4 0x0>;
				compatible = "pixcir,pixcir_tangoc";
			};
		};

		mmc@4809c000 {
			compatible = "ti,dra7-sdhci";
			reg = <0x4809c000 0x400>;
			interrupts = <0x0 0x4e 0x4>;
			ti,hwmods = "mmc1";
			status = "okay";
			pbias-supply = <0xd1>;
			max-frequency = <0xb71b000>;
			pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
			pinctrl-0 = <0xd2>;
			bus-width = <0x4>;
			pinctrl-1 = <0xd3>;
			pinctrl-2 = <0xd4>;
			pinctrl-3 = <0xd5>;
			pinctrl-4 = <0xd6>;
			pinctrl-5 = <0xd7 0xd8>;
			pinctrl-6 = <0xd9 0xda>;
			vmmc-supply = <0xcf>;
			phandle = <0x1d5>;
		};

		mmc@480b4000 {
			compatible = "ti,dra7-sdhci";
			reg = <0x480b4000 0x400>;
			interrupts = <0x0 0x51 0x4>;
			ti,hwmods = "mmc2";
			status = "disabled";
			max-frequency = <0xb71b000>;
			sdhci-caps-mask = <0x7 0x0>;
			mmc-hs200-1_8v;
			mmc-ddr-1_8v;
			pinctrl-names = "default", "hs", "ddr_1_8v";
			pinctrl-0 = <0xdb>;
			vmmc-supply = <0xcf>;
			vqmmc-supply = <0xcf>;
			bus-width = <0x8>;
			non-removable;
			no-1-8-v;
			pinctrl-1 = <0xdc>;
			pinctrl-2 = <0xdd>;
			phandle = <0x1d6>;
		};

		mmc@480ad000 {
			pinctrl-4 = <0x142 0x19d>;
			pinctrl-3 = <0x141>;
			pinctrl-2 = <0x140>;
			pinctrl-1 = <0x13f>;
			pinctrl-0 = <0x13e>;
			pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50";
			#size-cells = <0x0>;
			#address-cells = <0x1>;
			non-removable;
			keep-power-in-suspend;
			cap-power-off-card;
			bus-width = <0x4>;
			vqmmc-supply = <0x24a>;
			vmmc-supply = <0x249>;
			compatible = "ti,dra7-sdhci";
			reg = <0x480ad000 0x400>;
			interrupts = <0x0 0x59 0x4>;
			ti,hwmods = "mmc3";
			status = "disabled";
			max-frequency = <0x3d09000>;
			sdhci-caps-mask = <0x0 0x400000>;
			phandle = <0x1d7>;

			wlcore@2 {
				phandle = <0x24c>;
				interrupts = <0x7 0x1>;
				interrupt-parent = <0x1a3>;
				reg = <0x2>;
				compatible = "ti,wl1835";
			};
		};

		mmc@480d1000 {
			compatible = "ti,dra7-sdhci";
			reg = <0x480d1000 0x400>;
			interrupts = <0x0 0x5b 0x4>;
			ti,hwmods = "mmc4";
			status = "disabled";
			max-frequency = <0xb71b000>;
			sdhci-caps-mask = <0x0 0x400000>;
			phandle = <0x1d8>;
		};

		mmu@40d01000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x40d01000 0x100>;
			interrupts = <0x0 0x17 0x4>;
			ti,hwmods = "mmu0_dsp1";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0xde 0x0>;
			phandle = <0xc5>;
		};

		mmu@40d02000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x40d02000 0x100>;
			interrupts = <0x0 0x91 0x4>;
			ti,hwmods = "mmu1_dsp1";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0xde 0x1>;
			phandle = <0xc6>;
		};

		mmu@58882000 {
			compatible = "ti,dra7-iommu";
			reg = <0x58882000 0x100>;
			interrupts = <0x0 0x18b 0x4>;
			ti,hwmods = "mmu_ipu1";
			#iommu-cells = <0x0>;
			ti,iommu-bus-err-back;
			phandle = <0xb6>;
		};

		mmu@55082000 {
			compatible = "ti,dra7-iommu";
			reg = <0x55082000 0x100>;
			interrupts = <0x0 0x18c 0x4>;
			ti,hwmods = "mmu_ipu2";
			#iommu-cells = <0x0>;
			ti,iommu-bus-err-back;
			phandle = <0xbe>;
		};

		pruss_soc_bus@4b226004 {
			compatible = "ti,am5728-pruss-soc-bus";
			reg = <0x4b226004 0x4>;
			ti,hwmods = "pruss1";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4b200000 0x80000>;
			status = "okay";
			phandle = <0x1d9>;

			pruss@0 {
				compatible = "ti,am5728-pruss";
				reg = <0x0 0x80000>;
				interrupts = <0x0 0xba 0x4 0x0 0xbb 0x4 0x0 0xbc 0x4 0x0 0xbd 0x4 0x0 0xbe 0x4 0x0 0xbf 0x4 0x0 0xc0 0x4 0x0 0xc1 0x4>;
				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges;
				status = "okay";
				phandle = <0x1da>;

				memories@0 {
					reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x8000 0x2e000 0x31c 0x30000 0x60>;
					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
					phandle = <0x1db>;
				};

				cfg@26000 {
					compatible = "syscon";
					reg = <0x26000 0x2000>;
					phandle = <0x1dc>;
				};

				mii_rt@32000 {
					compatible = "syscon";
					reg = <0x32000 0x58>;
					phandle = <0x1dd>;
				};

				intc@20000 {
					compatible = "ti,am5728-pruss-intc";
					reg = <0x20000 0x2000>;
					reg-names = "intc";
					interrupt-controller;
					#interrupt-cells = <0x1>;
					phandle = <0xdf>;
				};

				pru@34000 {
					compatible = "ti,am5728-pru";
					reg = <0x34000 0x3000 0x22000 0x400 0x22400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am57xx-pru1_0-fw";
					interrupt-parent = <0xdf>;
					interrupts = <0x10 0x11>;
					interrupt-names = "vring", "kick";
					phandle = <0x1de>;
				};

				pru@38000 {
					compatible = "ti,am5728-pru";
					reg = <0x38000 0x3000 0x24000 0x400 0x24400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am57xx-pru1_1-fw";
					interrupt-parent = <0xdf>;
					interrupts = <0x12 0x13>;
					interrupt-names = "vring", "kick";
					phandle = <0x1df>;
				};

				mdio@32400 {
					compatible = "ti,davinci_mdio";
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					clocks = <0xe0>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					reg = <0x32400 0x90>;
					status = "disabled";
					phandle = <0x1e0>;
				};
			};
		};

		pruss_soc_bus@4b2a6004 {
			compatible = "ti,am5728-pruss-soc-bus";
			reg = <0x4b2a6004 0x4>;
			ti,hwmods = "pruss2";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges = <0x0 0x4b280000 0x80000>;
			status = "okay";
			phandle = <0x1e1>;

			pruss@0 {
				compatible = "ti,am5728-pruss";
				reg = <0x0 0x80000>;
				interrupts = <0x0 0xc4 0x4 0x0 0xc5 0x4 0x0 0xc6 0x4 0x0 0xc7 0x4 0x0 0xc8 0x4 0x0 0xc9 0x4 0x0 0xca 0x4 0x0 0xcb 0x4>;
				interrupt-names = "host2", "host3", "host4", "host5", "host6", "host7", "host8", "host9";
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				ranges;
				status = "okay";
				phandle = <0x1e2>;

				memories@0 {
					reg = <0x0 0x2000 0x2000 0x2000 0x10000 0x8000 0x2e000 0x31c 0x30000 0x60>;
					reg-names = "dram0", "dram1", "shrdram2", "iep", "ecap";
					phandle = <0x1e3>;
				};

				cfg@26000 {
					compatible = "syscon";
					reg = <0x26000 0x2000>;
					phandle = <0x1e4>;
				};

				iep@2e000 {
					compatible = "syscon";
					reg = <0x2e000 0x31c>;
					phandle = <0x1e5>;
				};

				mii_rt@32000 {
					compatible = "syscon";
					reg = <0x32000 0x58>;
					phandle = <0x1e6>;
				};

				intc@20000 {
					compatible = "ti,am5728-pruss-intc";
					reg = <0x20000 0x2000>;
					reg-names = "intc";
					interrupt-controller;
					#interrupt-cells = <0x1>;
					phandle = <0xe1>;
				};

				pru@34000 {
					compatible = "ti,am5728-pru";
					reg = <0x34000 0x3000 0x22000 0x400 0x22400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am57xx-pru2_0-fw";
					interrupt-parent = <0xe1>;
					interrupts = <0x10 0x11>;
					interrupt-names = "vring", "kick";
					phandle = <0x1e7>;
				};

				pru@38000 {
					compatible = "ti,am5728-pru";
					reg = <0x38000 0x3000 0x24000 0x400 0x24400 0x100>;
					reg-names = "iram", "control", "debug";
					firmware-name = "am57xx-pru2_1-fw";
					interrupt-parent = <0xe1>;
					interrupts = <0x12 0x13>;
					interrupt-names = "vring", "kick";
					phandle = <0x1e8>;
				};

				mdio@32400 {
					compatible = "ti,davinci_mdio";
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					clocks = <0xe0>;
					clock-names = "fck";
					bus_freq = <0xf4240>;
					reg = <0x32400 0x90>;
					status = "disabled";
					phandle = <0x1e9>;
				};
			};
		};

		regulator-abb-mpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_mpu";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0x11>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07ddc 0x4 0x4ae07de0 0x4 0x4ae06014 0x4 0x4a003b20 0xc 0x4ae0c158 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x80>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x102ca0 0x0 0x0 0x0 0x2000000 0x1f00000 0x11b340 0x0 0x4 0x0 0x2000000 0x1f00000 0x127690 0x0 0x8 0x0 0x2000000 0x1f00000>;
			phandle = <0x5>;
		};

		regulator-abb-ivahd {
			compatible = "ti,abb-v3";
			regulator-name = "abb_ivahd";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0x11>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07e34 0x4 0x4ae07e24 0x4 0x4ae06010 0x4 0x4a0025cc 0xc 0x4a002470 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x40000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
			phandle = <0x1ea>;
		};

		regulator-abb-dspeve {
			compatible = "ti,abb-v3";
			regulator-name = "abb_dspeve";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0x11>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07e30 0x4 0x4ae07e20 0x4 0x4ae06010 0x4 0x4a0025e0 0xc 0x4a00246c 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x20000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x101918 0x0 0x0 0x0 0x2000000 0x1f00000 0x118c30 0x0 0x4 0x0 0x2000000 0x1f00000 0x1312d0 0x0 0x8 0x0 0x2000000 0x1f00000>;
			phandle = <0x1eb>;
		};

		regulator-abb-gpu {
			compatible = "ti,abb-v3";
			regulator-name = "abb_gpu";
			#address-cells = <0x0>;
			#size-cells = <0x0>;
			clocks = <0x11>;
			ti,settling-time = <0x32>;
			ti,clock-cycles = <0x10>;
			reg = <0x4ae07de4 0x4 0x4ae07de8 0x4 0x4ae06010 0x4 0x4a003b08 0xc 0x4ae0c154 0x4>;
			reg-names = "setup-address", "control-address", "int-address", "efuse-address", "ldo-address";
			ti,tranxdone-status-mask = <0x10000000>;
			ti,ldovbb-override-mask = <0x400>;
			ti,ldovbb-vset-mask = <0x1f>;
			ti,abb_info = <0x10a1d0 0x0 0x0 0x0 0x2000000 0x1f00000 0x127690 0x0 0x4 0x0 0x2000000 0x1f00000 0x138800 0x0 0x8 0x0 0x2000000 0x1f00000>;
			phandle = <0x1ec>;
		};

		spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <0x0 0x3c 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <0x4>;
			dmas = <0xb4 0x23 0xb4 0x24 0xb4 0x25 0xb4 0x26 0xb4 0x27 0xb4 0x28 0xb4 0x29 0xb4 0x2a>;
			dma-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3", "rx3";
			status = "disabled";
			phandle = <0x1ed>;
		};

		spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <0x0 0x3d 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <0x2>;
			dmas = <0xb4 0x2b 0xb4 0x2c 0xb4 0x2d 0xb4 0x2e>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
			status = "disabled";
			phandle = <0x1ee>;
		};

		spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <0x0 0x56 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <0x2>;
			dmas = <0xb4 0xf 0xb4 0x10>;
			dma-names = "tx0", "rx0";
			status = "disabled";
			phandle = <0x1ef>;
		};

		spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <0x0 0x2b 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <0x1>;
			dmas = <0xb4 0x46 0xb4 0x47>;
			dma-names = "tx0", "rx0";
			status = "disabled";
			phandle = <0x1f0>;
		};

		qspi@4b300000 {
			compatible = "ti,dra7xxx-qspi";
			reg = <0x4b300000 0x100 0x5c000000 0x4000000>;
			reg-names = "qspi_base", "qspi_mmap";
			syscon-chipselects = <0x9 0x558>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			ti,hwmods = "qspi";
			clocks = <0xe2>;
			clock-names = "fck";
			num-cs = <0x4>;
			interrupts = <0x0 0x157 0x4>;
			status = "disabled";
			phandle = <0x1f1>;
		};

		ocp2scp@4a090000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x4a090000 0x20>;
			ti,hwmods = "ocp2scp3";

			phy@4A096000 {
				compatible = "ti,phy-pipe3-sata";
				reg = <0x4a096000 0x80 0x4a096400 0x64 0x4a096800 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				syscon-phy-power = <0x9 0x374>;
				clocks = <0x11 0xe3>;
				clock-names = "sysclk", "refclk";
				syscon-pllreset = <0x9 0x3fc>;
				#phy-cells = <0x0>;
				phandle = <0xea>;
			};

			pciephy@4a094000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a094000 0x80 0x4a094400 0x64>;
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <0xac 0x1c>;
				syscon-pcs = <0xac 0x10>;
				clocks = <0x59 0x5a 0xe4 0xe5 0xe6 0x5e 0x11>;
				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
				#phy-cells = <0x0>;
				phandle = <0xab>;
			};

			pciephy@4a095000 {
				compatible = "ti,phy-pipe3-pcie";
				reg = <0x4a095000 0x80 0x4a095400 0x64>;
				reg-names = "phy_rx", "phy_tx";
				syscon-phy-power = <0xac 0x20>;
				syscon-pcs = <0xac 0x10>;
				clocks = <0x59 0x5a 0xe7 0xe8 0xe9 0x5e 0x11>;
				clock-names = "dpll_ref", "dpll_ref_m2", "wkupclk", "refclk", "div-clk", "phy-div", "sysclk";
				#phy-cells = <0x0>;
				status = "disabled";
				phandle = <0xb0>;
			};
		};

		sata@4a141100 {
			compatible = "snps,dwc-ahci";
			reg = <0x4a140000 0x1100 0x4a141100 0x7>;
			interrupts = <0x0 0x31 0x4>;
			phys = <0xea>;
			phy-names = "sata-phy";
			clocks = <0xe3>;
			ti,hwmods = "sata";
			ports-implemented = <0x1>;
			status = "okay";
			phandle = <0x1f2>;
		};

		rtc@48838000 {
			compatible = "ti,am3352-rtc";
			reg = <0x48838000 0x100>;
			interrupts = <0x0 0xd9 0x4 0x0 0xd9 0x4>;
			ti,hwmods = "rtcss";
			clocks = <0x51>;
			phandle = <0x1f3>;
		};

		ocp2scp@4a080000 {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x4a080000 0x20>;
			ti,hwmods = "ocp2scp1";

			phy@4a084000 {
				compatible = "ti,dra7x-usb2", "ti,omap-usb2";
				reg = <0x4a084000 0x400>;
				syscon-phy-power = <0x9 0x300>;
				clocks = <0xeb 0xec>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0x0>;
				phy-supply = <0xed>;
				phandle = <0xf1>;
			};

			phy@4a085000 {
				compatible = "ti,dra7x-usb2-phy2", "ti,omap-usb2";
				reg = <0x4a085000 0x400>;
				syscon-phy-power = <0x9 0xe74>;
				clocks = <0xee 0xef>;
				clock-names = "wkupclk", "refclk";
				#phy-cells = <0x0>;
				phy-supply = <0xed>;
				phandle = <0xf4>;
			};

			phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80 0x4a084800 0x64 0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				syscon-phy-power = <0x9 0x370>;
				clocks = <0xf0 0x11 0xec>;
				clock-names = "wkupclk", "sysclk", "refclk";
				#phy-cells = <0x0>;
				phandle = <0xf2>;
			};
		};

		omap_dwc3_1@48880000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss1";
			reg = <0x48880000 0x10000>;
			interrupts = <0x0 0x48 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			phandle = <0x1f4>;

			usb@48890000 {
				compatible = "snps,dwc3";
				reg = <0x48890000 0x17000>;
				interrupts = <0x0 0x47 0x4 0x0 0x47 0x4 0x0 0x48 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				phys = <0xf1 0xf2>;
				phy-names = "usb2-phy", "usb3-phy";
				maximum-speed = "super-speed";
				dr_mode = "host";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
				phandle = <0x1f5>;
			};
		};

		omap_dwc3_2@488c0000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss2";
			reg = <0x488c0000 0x10000>;
			interrupts = <0x0 0x57 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			extcon = <0xf3>;
			phandle = <0x1f6>;

			usb@488d0000 {
				compatible = "snps,dwc3";
				reg = <0x488d0000 0x17000>;
				interrupts = <0x0 0x49 0x4 0x0 0x49 0x4 0x0 0x57 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				phys = <0xf4>;
				phy-names = "usb2-phy";
				maximum-speed = "high-speed";
				dr_mode = "peripheral";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
				snps,dis_metastability_quirk;
				phandle = <0x1f7>;
			};
		};

		omap_dwc3_3@48900000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss3";
			reg = <0x48900000 0x10000>;
			interrupts = <0x0 0x158 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			status = "disabled";
			phandle = <0x1f8>;

			usb@48910000 {
				compatible = "snps,dwc3";
				reg = <0x48910000 0x17000>;
				interrupts = <0x0 0x58 0x4 0x0 0x58 0x4 0x0 0x158 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				snps,dis_u3_susphy_quirk;
				snps,dis_u2_susphy_quirk;
				phandle = <0x1f9>;
			};
		};

		elm@48078000 {
			compatible = "ti,am3352-elm";
			reg = <0x48078000 0xfc0>;
			interrupts = <0x0 0x1 0x4>;
			ti,hwmods = "elm";
			status = "disabled";
			phandle = <0x1fa>;
		};

		gpmc@50000000 {
			compatible = "ti,am3352-gpmc";
			ti,hwmods = "gpmc";
			reg = <0x50000000 0x37c>;
			interrupts = <0x0 0xf 0x4>;
			dmas = <0xf5 0x4 0x0>;
			dma-names = "rxtx";
			gpmc,num-cs = <0x8>;
			gpmc,num-waitpins = <0x2>;
			#address-cells = <0x2>;
			#size-cells = <0x1>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			gpio-controller;
			#gpio-cells = <0x2>;
			status = "disabled";
			phandle = <0x1fb>;
		};

		atl@4843c000 {
			compatible = "ti,dra7-atl";
			reg = <0x4843c000 0x3ff>;
			ti,hwmods = "atl";
			ti,provided-clocks = <0x44 0x43 0x42 0x41>;
			clocks = <0x10>;
			clock-names = "fck";
			status = "disabled";
			phandle = <0x1fc>;
		};

		mcasp@48460000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp1";
			reg = <0x48460000 0x2000 0x45800000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x68 0x4 0x0 0x67 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf5 0x81 0x1 0xf5 0x80 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xf6 0xf7 0xf8>;
			clock-names = "fck", "ahclkx", "ahclkr";
			status = "disabled";
			phandle = <0x1fd>;
		};

		mcasp@48464000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp2";
			reg = <0x48464000 0x2000 0x45c00000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x95 0x4 0x0 0x94 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf5 0x83 0x1 0xf5 0x82 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xf9 0xfa 0xfb>;
			clock-names = "fck", "ahclkx", "ahclkr";
			status = "disabled";
			phandle = <0x1fe>;
		};

		mcasp@48468000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp3";
			reg = <0x48468000 0x2000 0x46000000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x97 0x4 0x0 0x96 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf5 0x85 0x1 0xf5 0x84 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xfc 0x78>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			#sound-dai-cells = <0x0>;
			assigned-clocks = <0x78>;
			assigned-clock-parents = <0x45>;
			op-mode = <0x0>;
			tdm-slots = <0x2>;
			serial-dir = <0x1 0x2 0x0 0x0>;
			tx-num-evt = <0x20>;
			rx-num-evt = <0x20>;
			phandle = <0x12e>;
		};

		mcasp@4846c000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp4";
			reg = <0x4846c000 0x2000 0x48436000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x99 0x4 0x0 0x98 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf5 0x87 0x1 0xf5 0x86 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xfd 0xfe>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x1ff>;
		};

		mcasp@48470000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp5";
			reg = <0x48470000 0x2000 0x4843a000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x9b 0x4 0x0 0x9a 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf5 0x89 0x1 0xf5 0x88 0x1>;
			dma-names = "tx", "rx";
			clocks = <0xff 0x100>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x200>;
		};

		mcasp@48474000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp6";
			reg = <0x48474000 0x2000 0x4844c000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x9d 0x4 0x0 0x9c 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf5 0x8b 0x1 0xf5 0x8a 0x1>;
			dma-names = "tx", "rx";
			clocks = <0x101 0x102>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x201>;
		};

		mcasp@48478000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp7";
			reg = <0x48478000 0x2000 0x48450000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0x9f 0x4 0x0 0x9e 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf5 0x8d 0x1 0xf5 0x8c 0x1>;
			dma-names = "tx", "rx";
			clocks = <0x103 0x104>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x202>;
		};

		mcasp@4847c000 {
			compatible = "ti,dra7-mcasp-audio";
			ti,hwmods = "mcasp8";
			reg = <0x4847c000 0x2000 0x48454000 0x1000>;
			reg-names = "mpu", "dat";
			interrupts = <0x0 0xa1 0x4 0x0 0xa0 0x4>;
			interrupt-names = "tx", "rx";
			dmas = <0xf5 0x8f 0x1 0xf5 0x8e 0x1>;
			dma-names = "tx", "rx";
			clocks = <0x105 0x106>;
			clock-names = "fck", "ahclkx";
			status = "disabled";
			phandle = <0x203>;
		};

		crossbar@4a002a48 {
			compatible = "ti,irq-crossbar";
			reg = <0x4a002a48 0x130>;
			interrupt-controller;
			interrupt-parent = <0x8>;
			#interrupt-cells = <0x3>;
			ti,max-irqs = <0xa0>;
			ti,max-crossbar-sources = <0x190>;
			ti,reg-size = <0x2>;
			ti,irqs-reserved = <0x0 0x1 0x2 0x3 0x5 0x6 0x83 0x84>;
			ti,irqs-skip = <0xa 0x85 0x8b 0x8c>;
			ti,irqs-safe-map = <0x0>;
			phandle = <0x1>;
		};

		ethernet@48484000 {
			compatible = "ti,dra7-cpsw", "ti,cpsw";
			ti,hwmods = "gmac";
			clocks = <0x107 0x108>;
			clock-names = "fck", "cpts";
			cpdma_channels = <0x8>;
			ale_entries = <0x400>;
			bd_ram_size = <0x2000>;
			mac_control = <0x20>;
			slaves = <0x2>;
			active_slave = <0x1>;
			cpts_clock_mult = <0x784cfe14>;
			cpts_clock_shift = <0x1d>;
			reg = <0x48484000 0x1000 0x48485200 0x2e00>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ti,no-idle;
			interrupts = <0x0 0x14e 0x4 0x0 0x14f 0x4 0x0 0x150 0x4 0x0 0x151 0x4>;
			ranges;
			syscon = <0x9>;
			status = "okay";
			dual_emac;
			phandle = <0x204>;

			mdio@48485000 {
				compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				ti,hwmods = "davinci_mdio";
				bus_freq = <0xf4240>;
				reg = <0x48485000 0x100>;
				phandle = <0x205>;

				ethernet-phy@0 {
					reg = <0x0>;
					phandle = <0x109>;
				};

				ethernet-phy@2 {
					reg = <0x2>;
					phandle = <0x10a>;
				};
			};

			slave@48480200 {
				mac-address = [00 00 00 00 00 00];
				phy-handle = <0x109>;
				phy-mode = "rgmii";
				dual_emac_res_vlan = <0x1>;
				phandle = <0x206>;
			};

			slave@48480300 {
				mac-address = [00 00 00 00 00 00];
				phy-handle = <0x10a>;
				phy-mode = "rgmii";
				dual_emac_res_vlan = <0x2>;
				phandle = <0x207>;
			};

			cpsw-phy-sel@4a002554 {
				compatible = "ti,dra7xx-cpsw-phy-sel";
				reg = <0x4a002554 0x4>;
				reg-names = "gmii-sel";
				phandle = <0x208>;
			};
		};

		can@4ae3c000 {
			compatible = "ti,dra7-d_can";
			ti,hwmods = "dcan1";
			reg = <0x4ae3c000 0x2000>;
			syscon-raminit = <0x9 0x558 0x0>;
			interrupts = <0x0 0xde 0x4>;
			clocks = <0x10b>;
			status = "disabled";
			phandle = <0x209>;
		};

		can@48480000 {
			compatible = "ti,dra7-d_can";
			ti,hwmods = "dcan2";
			reg = <0x48480000 0x2000>;
			syscon-raminit = <0x9 0x558 0x1>;
			interrupts = <0x0 0xe1 0x4>;
			clocks = <0x11>;
			status = "disabled";
			phandle = <0x20a>;
		};

		gpu@56000000 {
			compatible = "ti,dra7-sgx544", "img,sgx544";
			reg = <0x56000000 0x10000>;
			reg-names = "gpu_ocp_base";
			interrupts = <0x0 0x10 0x4>;
			ti,hwmods = "gpu";
			clocks = <0xa 0x75 0x76>;
			clock-names = "iclk", "fclk1", "fclk2";
			status = "ok";
			phandle = <0x20b>;
		};

		bb2d@59000000 {
			compatible = "ti,dra7-bb2d";
			reg = <0x59000000 0x700>;
			interrupts = <0x0 0x78 0x4>;
			ti,hwmods = "bb2d";
			clocks = <0x10c>;
			clock-names = "fclk";
			status = "okay";
			phandle = <0x20c>;
		};

		dss@58000000 {
			compatible = "ti,dra7-dss";
			status = "ok";
			ti,hwmods = "dss_core";
			syscon-pll-ctrl = <0x9 0x538>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			ranges;
			reg = <0x58000000 0x80 0x58004054 0x4 0x58004300 0x20 0x58009054 0x4 0x58009300 0x20>;
			reg-names = "dss", "pll1_clkctrl", "pll1", "pll2_clkctrl", "pll2";
			clocks = <0x10d 0x10e 0x10f>;
			clock-names = "fck", "video1_clk", "video2_clk";
			vdda_video-supply = <0x110>;
			phandle = <0x20d>;

			ports {
				#size-cells = <0x0>;
				#address-cells = <0x1>;

				port {
					reg = <0x0>;

					endpoint {
						phandle = <0x247>;
						remote-endpoint = <0x248>;
						data-lines = <0x18>;
					};
				};
			};

			dispc@58001000 {
				compatible = "ti,dra7-dispc";
				reg = <0x58001000 0x1000>;
				interrupts = <0x0 0x14 0x4>;
				ti,hwmods = "dss_dispc";
				clocks = <0x10d>;
				clock-names = "fck";
				syscon-pol = <0x9 0x534>;
			};

			encoder@58060000 {
				compatible = "ti,dra7-hdmi";
				reg = <0x58040000 0x200 0x58040200 0x80 0x58040300 0x80 0x58060000 0x19000>;
				reg-names = "wp", "pll", "phy", "core";
				interrupts = <0x0 0x60 0x4>;
				status = "ok";
				ti,hwmods = "dss_hdmi";
				clocks = <0x111 0x112>;
				clock-names = "fck", "sys_clk";
				dmas = <0xb4 0x4c>;
				dma-names = "audio_tx";
				vdda-supply = <0x113>;
				phandle = <0x20e>;

				port {

					endpoint {
						remote-endpoint = <0x114>;
						phandle = <0x12b>;
					};
				};
			};
		};

		epwmss@4843e000 {
			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
			reg = <0x4843e000 0x30>;
			ti,hwmods = "epwmss0";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "disabled";
			ranges;
			phandle = <0x20f>;

			pwm@4843e200 {
				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x4843e200 0x80>;
				clocks = <0x115 0xb>;
				clock-names = "tbclk", "fck";
				status = "disabled";
				phandle = <0x210>;
			};

			ecap@4843e100 {
				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
				#pwm-cells = <0x3>;
				reg = <0x4843e100 0x80>;
				clocks = <0xb>;
				clock-names = "fck";
				status = "disabled";
				phandle = <0x211>;
			};
		};

		epwmss@48440000 {
			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
			reg = <0x48440000 0x30>;
			ti,hwmods = "epwmss1";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "okay";
			ranges;
			phandle = <0x212>;

			pwm@48440200 {
				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x48440200 0x80>;
				clocks = <0x116 0xb>;
				clock-names = "tbclk", "fck";
				status = "okay";
				phandle = <0x213>;
			};

			ecap@48440100 {
				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
				#pwm-cells = <0x3>;
				reg = <0x48440100 0x80>;
				clocks = <0xb>;
				clock-names = "fck";
				status = "disabled";
				phandle = <0x214>;
			};
		};

		epwmss@48442000 {
			compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
			reg = <0x48442000 0x30>;
			ti,hwmods = "epwmss2";
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			status = "disabled";
			ranges;
			phandle = <0x215>;

			pwm@48442200 {
				compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
				#pwm-cells = <0x3>;
				reg = <0x48442200 0x80>;
				clocks = <0x117 0xb>;
				clock-names = "tbclk", "fck";
				status = "disabled";
				phandle = <0x216>;
			};

			ecap@48442100 {
				compatible = "ti,dra746-ecap", "ti,am3352-ecap";
				#pwm-cells = <0x3>;
				reg = <0x48442100 0x80>;
				clocks = <0xb>;
				clock-names = "fck";
				status = "disabled";
				phandle = <0x217>;
			};
		};

		aes@4b500000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes1";
			reg = <0x4b500000 0xa0>;
			interrupts = <0x0 0x50 0x4>;
			dmas = <0xf5 0x6f 0x0 0xf5 0x6e 0x0>;
			dma-names = "tx", "rx";
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x218>;
		};

		aes@4b700000 {
			compatible = "ti,omap4-aes";
			ti,hwmods = "aes2";
			reg = <0x4b700000 0xa0>;
			interrupts = <0x0 0x3b 0x4>;
			dmas = <0xf5 0x72 0x0 0xf5 0x71 0x0>;
			dma-names = "tx", "rx";
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x219>;
		};

		des@480a5000 {
			compatible = "ti,omap4-des";
			ti,hwmods = "des";
			reg = <0x480a5000 0xa0>;
			interrupts = <0x0 0x4d 0x4>;
			dmas = <0xb4 0x75 0xb4 0x74>;
			dma-names = "tx", "rx";
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x21a>;
		};

		sham@53100000 {
			compatible = "ti,omap5-sham";
			ti,hwmods = "sham";
			reg = <0x4b101000 0x300>;
			interrupts = <0x0 0x2e 0x4>;
			dmas = <0xf5 0x77 0x0>;
			dma-names = "rx";
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x21b>;
		};

		rng@48090000 {
			compatible = "ti,omap4-rng";
			ti,hwmods = "rng";
			reg = <0x48090000 0x2000>;
			interrupts = <0x0 0x2f 0x4>;
			clocks = <0xa>;
			clock-names = "fck";
			phandle = <0x21c>;
		};

		opp-supply@4a003b20 {
			compatible = "ti,omap5-opp-supply";
			reg = <0x4a003b20 0xc>;
			ti,efuse-settings = <0x102ca0 0x0 0x11b340 0x4 0x127690 0x8>;
			ti,absolute-max-voltage-uv = <0x16e360>;
			phandle = <0x21d>;
		};

		vpe {
			compatible = "ti,vpe";
			ti,hwmods = "vpe";
			clocks = <0x81>;
			clock-names = "fck";
			reg = <0x489d0000 0x120 0x489d0300 0x20 0x489d0400 0x20 0x489d0500 0x20 0x489d0600 0x3c 0x489d0700 0x80 0x489d5700 0x18 0x489dd000 0x400>;
			reg-names = "vpe_top", "vpe_chr_us0", "vpe_chr_us1", "vpe_chr_us2", "vpe_dei", "sc", "csc", "vpdma";
			interrupts = <0x0 0x162 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		vip@0x48970000 {
			compatible = "ti,vip1";
			reg = <0x48970000 0x114 0x48975500 0xd8 0x48975700 0x18 0x48975800 0x80 0x48975a00 0xd8 0x48975c00 0x18 0x48975d00 0x80 0x4897d000 0x400>;
			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
			ti,hwmods = "vip1";
			interrupts = <0x0 0x15f 0x4 0x0 0x188 0x4>;
			syscon-pol = <0x9 0x534>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
			phandle = <0x21e>;

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
				phandle = <0x21f>;
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
				phandle = <0x220>;
			};

			port@2 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x2>;
				status = "disabled";
				phandle = <0x221>;
			};

			port@3 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x3>;
				status = "disabled";
				phandle = <0x222>;
			};
		};

		dsp_system@41500000 {
			compatible = "syscon";
			reg = <0x41500000 0x100>;
			phandle = <0x118>;
		};

		omap_dwc3_4@48940000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss4";
			reg = <0x48940000 0x10000>;
			interrupts = <0x0 0x15a 0x4>;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			utmi-mode = <0x2>;
			ranges;
			status = "disabled";
			phandle = <0x223>;

			usb@48950000 {
				compatible = "snps,dwc3";
				reg = <0x48950000 0x17000>;
				interrupts = <0x0 0x159 0x4 0x0 0x159 0x4 0x0 0x15a 0x4>;
				interrupt-names = "peripheral", "host", "otg";
				maximum-speed = "high-speed";
				dr_mode = "otg";
				phandle = <0x224>;
			};
		};

		mmu@41501000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x41501000 0x100>;
			interrupts = <0x0 0x92 0x4>;
			ti,hwmods = "mmu0_dsp2";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0x118 0x0>;
			phandle = <0x119>;
		};

		mmu@41502000 {
			compatible = "ti,dra7-dsp-iommu";
			reg = <0x41502000 0x100>;
			interrupts = <0x0 0x93 0x4>;
			ti,hwmods = "mmu1_dsp2";
			#iommu-cells = <0x0>;
			ti,syscon-mmuconfig = <0x118 0x1>;
			phandle = <0x11a>;
		};

		dsp@41000000 {
			compatible = "ti,dra7-dsp";
			reg = <0x41000000 0x48000 0x41600000 0x8000 0x41700000 0x8000>;
			reg-names = "l2ram", "l1pram", "l1dram";
			ti,hwmods = "dsp2";
			syscon-bootreg = <0x9 0x560>;
			iommus = <0x119 0x11a>;
			ti,rproc-standby-info = <0x4a005620>;
			status = "okay";
			mboxes = <0xbf 0x11b>;
			timers = <0x11c>;
			watchdog-timers = <0x11d>;
			memory-region = <0x11e>;
			phandle = <0x225>;
		};

		vip@0x48990000 {
			compatible = "ti,vip2";
			reg = <0x48990000 0x114 0x48995500 0xd8 0x48995700 0x18 0x48995800 0x80 0x48995a00 0xd8 0x48995c00 0x18 0x48995d00 0x80 0x4899d000 0x400>;
			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
			ti,hwmods = "vip2";
			interrupts = <0x0 0x160 0x4 0x0 0x189 0x4>;
			syscon-pol = <0x9 0x534>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
			phandle = <0x226>;

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
				phandle = <0x227>;
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
				phandle = <0x228>;
			};

			port@2 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x2>;
				status = "disabled";
				phandle = <0x229>;
			};

			port@3 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x3>;
				status = "disabled";
				phandle = <0x22a>;
			};
		};

		vip@0x489b0000 {
			compatible = "ti,vip3";
			reg = <0x489b0000 0x114 0x489b5500 0xd8 0x489b5700 0x18 0x489b5800 0x80 0x489b5a00 0xd8 0x489b5c00 0x18 0x489b5d00 0x80 0x489bd000 0x400>;
			reg-names = "vip", "parser0", "csc0", "sc0", "parser1", "csc1", "sc1", "vpdma";
			ti,hwmods = "vip3";
			interrupts = <0x0 0x161 0x4 0x0 0x18a 0x4>;
			syscon-pol = <0x9 0x534>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "disabled";
			phandle = <0x22b>;

			port@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x0>;
				status = "disabled";
				phandle = <0x22c>;
			};

			port@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x1>;
				status = "disabled";
				phandle = <0x22d>;
			};
		};
	};

	thermal-zones {
		phandle = <0x22e>;

		cpu_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x11f 0x0>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x22f>;

			trips {
				phandle = <0x230>;

				cpu_alert {
					temperature = <0x13880>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x120>;
				};

				cpu_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x231>;
				};

				cpu_alert1 {
					temperature = <0xc350>;
					hysteresis = <0x7d0>;
					type = "active";
					phandle = <0x122>;
				};
			};

			cooling-maps {
				phandle = <0x232>;

				map0 {
					trip = <0x120>;
					cooling-device = <0x121 0xffffffff 0xffffffff>;
				};

				map1 {
					trip = <0x122>;
					cooling-device = <0x123 0xffffffff 0xffffffff>;
				};
			};
		};

		gpu_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x11f 0x1>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x233>;

			trips {

				gpu_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x234>;
				};
			};
		};

		core_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x11f 0x2>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x235>;

			trips {

				core_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x236>;
				};
			};
		};

		dspeve_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x11f 0x3>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x237>;

			trips {

				dspeve_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x238>;
				};
			};
		};

		iva_thermal {
			polling-delay-passive = <0xfa>;
			polling-delay = <0x1f4>;
			thermal-sensors = <0x11f 0x4>;
			coefficients = <0x0 0x7d0>;
			phandle = <0x239>;

			trips {

				iva_crit {
					temperature = <0x15f90>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x23a>;
				};
			};
		};

		board_thermal {
			polling-delay-passive = <0x4e2>;
			polling-delay = <0x5dc>;
			thermal-sensors = <0x124 0x0>;
			phandle = <0x23b>;

			trips {
				phandle = <0x23c>;

				board_alert {
					temperature = <0x9c40>;
					hysteresis = <0x7d0>;
					type = "active";
					phandle = <0x125>;
				};

				board_crit {
					temperature = <0x19a28>;
					hysteresis = <0x0>;
					type = "critical";
					phandle = <0x23d>;
				};
			};

			cooling-maps {
				phandle = <0x23e>;

				map0 {
					trip = <0x125>;
					cooling-device = <0x123 0xffffffff 0xffffffff>;
				};
			};
		};
	};

	pmu {
		compatible = "arm,cortex-a15-pmu";
		interrupt-parent = <0x8>;
		interrupts = <0x0 0x83 0x4 0x0 0x84 0x4>;
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x80000000>;
	};

	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		ipu2-memory@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
			phandle = <0xc4>;
		};

		dsp1-memory@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
			phandle = <0xca>;
		};

		ipu1-memory@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
			phandle = <0xbd>;
		};

		dsp2-memory@9f000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9f000000 0x0 0x800000>;
			reusable;
			status = "okay";
			phandle = <0x11e>;
		};

		cmem_block_mem@a0000000 {
			reg = <0x0 0xa0000000 0x0 0xc000000>;
			no-map;
			status = "okay";
			phandle = <0x131>;
		};

		cmem_block_mem@40500000 {
			reg = <0x0 0x40500000 0x0 0x100000>;
			no-map;
			status = "okay";
			phandle = <0x132>;
		};
	};

	fixedregulator-main_12v0 {
		compatible = "regulator-fixed";
		regulator-name = "main_12v0";
		regulator-min-microvolt = <0xb71b00>;
		regulator-max-microvolt = <0xb71b00>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x126>;
	};

	fixedregulator-evm_5v0 {
		compatible = "regulator-fixed";
		regulator-name = "evm_5v0";
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		vin-supply = <0x126>;
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x23f>;
	};

	fixedregulator-vdd_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vdd_3v3";
		vin-supply = <0x127>;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		phandle = <0xcf>;
	};

	fixedregulator-aic_dvdd {
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd_fixed";
		vin-supply = <0xcf>;
		regulator-min-microvolt = <0x1b7740>;
		regulator-max-microvolt = <0x1b7740>;
		phandle = <0xd0>;
	};

	fixedregulator-vtt {
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		vin-supply = <0x128>;
		regulator-min-microvolt = <0x325aa0>;
		regulator-max-microvolt = <0x325aa0>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <0xce 0xb 0x0>;
		phandle = <0x240>;
	};

	leds {
		compatible = "gpio-leds";

		led0 {
			label = "beagle-x15:usr0";
			gpios = <0xce 0x9 0x0>;
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};

		led1 {
			label = "beagle-x15:usr1";
			gpios = <0xce 0x8 0x0>;
			linux,default-trigger = "cpu0";
			default-state = "off";
		};

		led2 {
			label = "beagle-x15:usr2";
			gpios = <0xce 0xe 0x0>;
			linux,default-trigger = "mmc0";
			default-state = "off";
		};

		led3 {
			label = "beagle-x15:usr3";
			gpios = <0xce 0xf 0x0>;
			linux,default-trigger = "disk-activity";
			default-state = "off";
		};
	};

	gpio_fan {
		compatible = "gpio-fan";
		gpios = <0x129 0x2 0x0>;
		gpio-fan,speed-map = <0x0 0x0 0x32c8 0x1>;
		#cooling-cells = <0x2>;
		phandle = <0x123>;
	};

	connector {
		compatible = "hdmi-connector";
		label = "hdmi";
		type = [61 00];
		phandle = <0x241>;

		port {

			endpoint {
				remote-endpoint = <0x12a>;
				phandle = <0x12c>;
			};
		};
	};

	encoder {
		compatible = "ti,tpd12s015";
		gpios = <0xce 0xa 0x0 0xaf 0x1e 0x0 0xce 0xc 0x0>;
		phandle = <0x242>;

		ports {
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			port@0 {
				reg = <0x0>;

				endpoint {
					remote-endpoint = <0x12b>;
					phandle = <0x114>;
				};
			};

			port@1 {
				reg = <0x1>;

				endpoint {
					remote-endpoint = <0x12c>;
					phandle = <0x12a>;
				};
			};
		};
	};

	sound0 {
		status = "disabled";
		compatible = "simple-audio-card";
		simple-audio-card,name = "BeagleBoard-X15";
		simple-audio-card,widgets = "Line", "Line Out", "Line", "Line In";
		simple-audio-card,routing = "Line Out", "LLOUT", "Line Out", "RLOUT", "MIC2L", "Line In", "MIC2R", "Line In";
		simple-audio-card,format = "dsp_b";
		simple-audio-card,bitclock-master = <0x12d>;
		simple-audio-card,frame-master = <0x12d>;
		simple-audio-card,bitclock-inversion;
		phandle = <0x243>;

		simple-audio-card,cpu {
			sound-dai = <0x12e>;
			status = "disabled";
		};

		simple-audio-card,codec {
			sound-dai = <0x12f>;
			clocks = <0x130>;
			phandle = <0x12d>;
		};
	};

	cmem {
		compatible = "ti,cmem";
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		#pool-size-cells = <0x2>;
		status = "okay";

		cmem_block@0 {
			reg = <0x0>;
			memory-region = <0x131>;
			cmem-buf-pools = <0x1 0x0 0xc000000>;
			phandle = <0x244>;
		};

		cmem_block@1 {
			reg = <0x1>;
			memory-region = <0x132>;
			phandle = <0x245>;
		};
	};

	__symbols__ {
		wlcore = "/ocp/mmc@480ad000/wlcore@2", "";
		dpi_out = "/ocp/dss@58000000/ports/port/endpoint", "";
		vmmcwl_fixed = "/fixedregulator-mmcwl", "";
		com_3v6 = "/fixedregulator-com_3v6", "";
		lcd_bl = "/backlight", "";
		lcd_in = "/display/port/endpoint", "";
		lcd0 = "/display", "";
		gic = "/interrupt-controller@48211000";
		wakeupgen = "/interrupt-controller@48281000";
		cpu0 = "/cpus/cpu@0";
		cpu0_opp_table = "/opp-table";
		l4_cfg = "/ocp/l4@4a000000";
		scm = "/ocp/l4@4a000000/scm@2000";
		scm_conf = "/ocp/l4@4a000000/scm@2000/scm_conf@0";
		pbias_regulator = "/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00";
		pbias_mmc_reg = "/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5";
		scm_conf_clocks = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks";
		dss_deshdcp_clk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dss_deshdcp_clk@558";
		ehrpwm0_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm0_tbclk@558";
		ehrpwm1_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm1_tbclk@558";
		ehrpwm2_tbclk = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm2_tbclk@558";
		sys_32k_ck = "/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/sys_32k_ck";
		dra7_pmx_core = "/ocp/l4@4a000000/scm@2000/pinmux@1400";
		mmc1_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default";
		mmc1_pins_default_no_clk_pu = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default_no_clk_pu";
		mmc1_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr12";
		mmc1_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_hs";
		mmc1_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr25";
		mmc1_pins_sdr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr50";
		mmc1_pins_ddr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_ddr50";
		mmc1_pins_sdr104 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr104";
		mmc2_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_default";
		mmc2_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs";
		mmc2_pins_ddr_3_3v_rev11 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_3_3v_rev11";
		mmc2_pins_ddr_1_8v_rev11 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_1_8v_rev11";
		mmc2_pins_ddr_rev20 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_rev20";
		mmc2_pins_hs200 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs200";
		mmc4_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_default";
		mmc4_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_hs";
		mmc3_pins_default = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_default";
		mmc3_pins_hs = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_hs";
		mmc3_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr12";
		mmc3_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr25";
		mmc3_pins_sdr50 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr50";
		mmc4_pins_sdr12 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr12";
		mmc4_pins_sdr25 = "/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr25";
		scm_conf1 = "/ocp/l4@4a000000/scm@2000/scm_conf@1c04";
		scm_conf_pcie = "/ocp/l4@4a000000/scm@2000/scm_conf@1c24";
		sdma_xbar = "/ocp/l4@4a000000/scm@2000/dma-router@b78";
		edma_xbar = "/ocp/l4@4a000000/scm@2000/dma-router@c78";
		cm_core_aon = "/ocp/l4@4a000000/cm_core_aon@5000";
		cm_core_aon_clocks = "/ocp/l4@4a000000/cm_core_aon@5000/clocks";
		atl_clkin0_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin0_ck";
		atl_clkin1_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin1_ck";
		atl_clkin2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin2_ck";
		atl_clkin3_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin3_ck";
		hdmi_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clkin_ck";
		mlb_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlb_clkin_ck";
		mlbp_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlbp_clkin_ck";
		pciesref_acs_clk_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/pciesref_acs_clk_ck";
		ref_clkin0_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin0_ck";
		ref_clkin1_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin1_ck";
		ref_clkin2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin2_ck";
		ref_clkin3_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin3_ck";
		rmii_clk_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/rmii_clk_ck";
		sdvenc_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sdvenc_clkin_ck";
		secure_32k_clk_src_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/secure_32k_clk_src_ck";
		sys_clk32_crystal_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_crystal_ck";
		sys_clk32_pseudo_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_pseudo_ck";
		virt_12000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_12000000_ck";
		virt_13000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_13000000_ck";
		virt_16800000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_16800000_ck";
		virt_19200000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_19200000_ck";
		virt_20000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_20000000_ck";
		virt_26000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_26000000_ck";
		virt_27000000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_27000000_ck";
		virt_38400000_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_38400000_ck";
		sys_clkin2 = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clkin2";
		usb_otg_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_otg_clkin_ck";
		video1_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clkin_ck";
		video1_m2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_m2_clkin_ck";
		video2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clkin_ck";
		video2_m2_clkin_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_m2_clkin_ck";
		dpll_abe_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_ck@1e0";
		dpll_abe_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_x2_ck";
		dpll_abe_m2x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2x2_ck@1f0";
		abe_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/abe_clk@108";
		dpll_abe_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2_ck@1f0";
		dpll_abe_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m3x2_ck@1f4";
		dpll_core_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_byp_mux@12c";
		dpll_core_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_ck@120";
		dpll_core_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_x2_ck";
		dpll_core_h12x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h12x2_ck@13c";
		mpu_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dpll_hs_clk_div";
		dpll_mpu_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_ck@160";
		dpll_mpu_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_m2_ck@170";
		mpu_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dclk_div";
		dsp_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dsp_dpll_hs_clk_div";
		dpll_dsp_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_byp_mux@240";
		dpll_dsp_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_ck@234";
		dpll_dsp_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m2_ck@244";
		iva_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dpll_hs_clk_div";
		dpll_iva_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_byp_mux@1ac";
		dpll_iva_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_ck@1a0";
		dpll_iva_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_m2_ck@1b0";
		iva_dclk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dclk";
		dpll_gpu_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_byp_mux@2e4";
		dpll_gpu_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_ck@2d8";
		dpll_gpu_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_m2_ck@2e8";
		dpll_core_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_m2_ck@130";
		core_dpll_out_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/core_dpll_out_dclk_div";
		dpll_ddr_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_byp_mux@21c";
		dpll_ddr_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_ck@210";
		dpll_ddr_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_m2_ck@220";
		dpll_gmac_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_byp_mux@2b4";
		dpll_gmac_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_ck@2a8";
		dpll_gmac_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m2_ck@2b8";
		video2_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_dclk_div";
		video1_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_dclk_div";
		hdmi_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_dclk_div";
		per_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/per_dpll_hs_clk_div";
		usb_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_dpll_hs_clk_div";
		eve_dpll_hs_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dpll_hs_clk_div";
		dpll_eve_byp_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_byp_mux@290";
		dpll_eve_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_ck@284";
		dpll_eve_m2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_m2_ck@294";
		eve_dclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dclk_div";
		dpll_core_h13x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h13x2_ck@140";
		dpll_core_h14x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h14x2_ck@144";
		dpll_core_h22x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h22x2_ck@154";
		dpll_core_h23x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h23x2_ck@158";
		dpll_core_h24x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h24x2_ck@15c";
		dpll_ddr_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_x2_ck";
		dpll_ddr_h11x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_h11x2_ck@228";
		dpll_dsp_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_x2_ck";
		dpll_dsp_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m3x2_ck@248";
		dpll_gmac_x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_x2_ck";
		dpll_gmac_h11x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h11x2_ck@2c0";
		dpll_gmac_h12x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h12x2_ck@2c4";
		dpll_gmac_h13x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h13x2_ck@2c8";
		dpll_gmac_m3x2_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m3x2_ck@2bc";
		gmii_m_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/gmii_m_clk_div";
		hdmi_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clk2_div";
		hdmi_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_div_clk";
		l3_iclk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/l3_iclk_div@100";
		l4_root_clk_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/l4_root_clk_div";
		video1_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clk2_div";
		video1_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_div_clk";
		video2_clk2_div = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clk2_div";
		video2_div_clk = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_div_clk";
		ipu1_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/ipu1_gfclk_mux@520";
		mcasp1_ahclkr_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_ahclkr_mux@550";
		mcasp1_ahclkx_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_ahclkx_mux@550";
		mcasp1_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mcasp1_aux_gfclk_mux@550";
		timer5_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer5_gfclk_mux@558";
		timer6_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer6_gfclk_mux@560";
		timer7_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer7_gfclk_mux@568";
		timer8_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/timer8_gfclk_mux@570";
		uart6_gfclk_mux = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/uart6_gfclk_mux@580";
		dummy_ck = "/ocp/l4@4a000000/cm_core_aon@5000/clocks/dummy_ck";
		cm_core_aon_clockdomains = "/ocp/l4@4a000000/cm_core_aon@5000/clockdomains";
		cm_core = "/ocp/l4@4a000000/cm_core@8000";
		cm_core_clocks = "/ocp/l4@4a000000/cm_core@8000/clocks";
		dpll_pcie_ref_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_ck@200";
		dpll_pcie_ref_m2ldo_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2ldo_ck@210";
		apll_pcie_in_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_in_clk_mux@4ae06118";
		apll_pcie_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_ck@21c";
		optfclk_pciephy1_32khz = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_32khz@4a0093b0";
		optfclk_pciephy2_32khz = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_32khz@4a0093b8";
		optfclk_pciephy_div = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy_div@4a00821c";
		optfclk_pciephy1_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_clk@4a0093b0";
		optfclk_pciephy2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_clk@4a0093b8";
		optfclk_pciephy1_div_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy1_div_clk@4a0093b0";
		optfclk_pciephy2_div_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy2_div_clk@4a0093b8";
		apll_pcie_clkvcoldo = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo";
		apll_pcie_clkvcoldo_div = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo_div";
		apll_pcie_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_m2_ck";
		dpll_per_byp_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_byp_mux@14c";
		dpll_per_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_ck@140";
		dpll_per_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2_ck@150";
		func_96m_aon_dclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_aon_dclk_div";
		dpll_usb_byp_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_byp_mux@18c";
		dpll_usb_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_ck@180";
		dpll_usb_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_m2_ck@190";
		dpll_pcie_ref_m2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2_ck@210";
		dpll_per_x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_x2_ck";
		dpll_per_h11x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h11x2_ck@158";
		dpll_per_h12x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h12x2_ck@15c";
		dpll_per_h13x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h13x2_ck@160";
		dpll_per_h14x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h14x2_ck@164";
		dpll_per_m2x2_ck = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2x2_ck@150";
		dpll_usb_clkdcoldo = "/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_clkdcoldo";
		func_128m_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_128m_clk";
		func_12m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_12m_fclk";
		func_24m_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_24m_clk";
		func_48m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_48m_fclk";
		func_96m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_fclk";
		l3init_60m_fclk = "/ocp/l4@4a000000/cm_core@8000/clocks/l3init_60m_fclk@104";
		clkout2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/clkout2_clk@6b0";
		l3init_960m_gfclk = "/ocp/l4@4a000000/cm_core@8000/clocks/l3init_960m_gfclk@6c0";
		dss_32khz_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_32khz_clk@1120";
		dss_48mhz_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_48mhz_clk@1120";
		dss_dss_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_dss_clk@1120";
		dss_hdmi_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_hdmi_clk@1120";
		dss_video1_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_video1_clk@1120";
		dss_video2_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/dss_video2_clk@1120";
		gpio2_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio2_dbclk@1760";
		gpio3_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio3_dbclk@1768";
		gpio4_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio4_dbclk@1770";
		gpio5_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio5_dbclk@1778";
		gpio6_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio6_dbclk@1780";
		gpio7_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio7_dbclk@1810";
		gpio8_dbclk = "/ocp/l4@4a000000/cm_core@8000/clocks/gpio8_dbclk@1818";
		mmc1_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_clk32k@1328";
		mmc2_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_clk32k@1330";
		mmc3_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_clk32k@1820";
		mmc4_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_clk32k@1828";
		sata_ref_clk = "/ocp/l4@4a000000/cm_core@8000/clocks/sata_ref_clk@1388";
		usb_otg_ss1_refclk960m = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_otg_ss1_refclk960m@13f0";
		usb_otg_ss2_refclk960m = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_otg_ss2_refclk960m@1340";
		usb_phy1_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy1_always_on_clk32k@640";
		usb_phy2_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy2_always_on_clk32k@688";
		usb_phy3_always_on_clk32k = "/ocp/l4@4a000000/cm_core@8000/clocks/usb_phy3_always_on_clk32k@698";
		atl_dpll_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/atl_dpll_clk_mux@c00";
		atl_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/atl_gfclk_mux@c00";
		rmii_50mhz_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/rmii_50mhz_clk_mux@13d0";
		gmac_rft_clk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gmac_rft_clk_mux@13d0";
		gpu_core_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gpu_core_gclk_mux@1220";
		gpu_hyd_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/gpu_hyd_gclk_mux@1220";
		l3instr_ts_gclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/l3instr_ts_gclk_div@e50";
		mcasp2_ahclkr_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_ahclkr_mux@1860";
		mcasp2_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_ahclkx_mux@1860";
		mcasp2_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp2_aux_gfclk_mux@1860";
		mcasp3_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp3_ahclkx_mux@1868";
		mcasp3_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp3_aux_gfclk_mux@1868";
		mcasp4_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp4_ahclkx_mux@1898";
		mcasp4_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp4_aux_gfclk_mux@1898";
		mcasp5_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp5_ahclkx_mux@1878";
		mcasp5_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp5_aux_gfclk_mux@1878";
		mcasp6_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp6_ahclkx_mux@1904";
		mcasp6_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp6_aux_gfclk_mux@1904";
		mcasp7_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp7_ahclkx_mux@1908";
		mcasp7_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp7_aux_gfclk_mux@1908";
		mcasp8_ahclkx_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp8_ahclkx_mux@1890";
		mcasp8_aux_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mcasp8_aux_gfclk_mux@1890";
		mmc1_fclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_fclk_mux@1328";
		mmc1_fclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc1_fclk_div@1328";
		mmc2_fclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_fclk_mux@1330";
		mmc2_fclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc2_fclk_div@1330";
		mmc3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_gfclk_mux@1820";
		mmc3_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc3_gfclk_div@1820";
		mmc4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_gfclk_mux@1828";
		mmc4_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/mmc4_gfclk_div@1828";
		qspi_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/qspi_gfclk_mux@1838";
		qspi_gfclk_div = "/ocp/l4@4a000000/cm_core@8000/clocks/qspi_gfclk_div@1838";
		timer10_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer10_gfclk_mux@1728";
		timer11_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer11_gfclk_mux@1730";
		timer13_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer13_gfclk_mux@17c8";
		timer14_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer14_gfclk_mux@17d0";
		timer15_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer15_gfclk_mux@17d8";
		timer16_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer16_gfclk_mux@1830";
		timer2_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer2_gfclk_mux@1738";
		timer3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer3_gfclk_mux@1740";
		timer4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer4_gfclk_mux@1748";
		timer9_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/timer9_gfclk_mux@1750";
		uart1_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart1_gfclk_mux@1840";
		uart2_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart2_gfclk_mux@1848";
		uart3_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart3_gfclk_mux@1850";
		uart4_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart4_gfclk_mux@1858";
		uart5_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart5_gfclk_mux@1870";
		uart7_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart7_gfclk_mux@18d0";
		uart8_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart8_gfclk_mux@18e0";
		uart9_gfclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/uart9_gfclk_mux@18e8";
		vip1_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip1_gclk_mux@1020";
		vip2_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip2_gclk_mux@1028";
		vip3_gclk_mux = "/ocp/l4@4a000000/cm_core@8000/clocks/vip3_gclk_mux@1030";
		cm_core_clockdomains = "/ocp/l4@4a000000/cm_core@8000/clockdomains";
		coreaon_clkdm = "/ocp/l4@4a000000/cm_core@8000/clockdomains/coreaon_clkdm";
		l4_wkup = "/ocp/l4@4ae00000";
		counter32k = "/ocp/l4@4ae00000/counter@4000";
		prm = "/ocp/l4@4ae00000/prm@6000";
		prm_clocks = "/ocp/l4@4ae00000/prm@6000/clocks";
		sys_clkin1 = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clkin1@110";
		abe_dpll_sys_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_sys_clk_mux@118";
		abe_dpll_bypass_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_bypass_clk_mux@114";
		abe_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_clk_mux@10c";
		abe_24m_fclk = "/ocp/l4@4ae00000/prm@6000/clocks/abe_24m_fclk@11c";
		aess_fclk = "/ocp/l4@4ae00000/prm@6000/clocks/aess_fclk@178";
		abe_giclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_giclk_div@174";
		abe_lp_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_lp_clk_div@1d8";
		abe_sys_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/abe_sys_clk_div@120";
		adc_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/adc_gfclk_mux@1dc";
		sys_clk1_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clk1_dclk_div@1c8";
		sys_clk2_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sys_clk2_dclk_div@1cc";
		per_abe_x1_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_dclk_div@1bc";
		dsp_gclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/dsp_gclk_div@18c";
		gpu_dclk = "/ocp/l4@4ae00000/prm@6000/clocks/gpu_dclk@1a0";
		emif_phy_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/emif_phy_dclk_div@190";
		gmac_250m_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/gmac_250m_dclk_div@19c";
		gmac_main_clk = "/ocp/l4@4ae00000/prm@6000/clocks/gmac_main_clk";
		l3init_480m_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/l3init_480m_dclk_div@1ac";
		usb_otg_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/usb_otg_dclk_div@184";
		sata_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/sata_dclk_div@1c0";
		pcie2_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/pcie2_dclk_div@1b8";
		pcie_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/pcie_dclk_div@1b4";
		emu_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/emu_dclk_div@194";
		secure_32k_dclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/secure_32k_dclk_div@1c4";
		clkoutmux0_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux0_clk_mux@158";
		clkoutmux1_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux1_clk_mux@15c";
		clkoutmux2_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux2_clk_mux@160";
		custefuse_sys_gfclk_div = "/ocp/l4@4ae00000/prm@6000/clocks/custefuse_sys_gfclk_div";
		eve_clk = "/ocp/l4@4ae00000/prm@6000/clocks/eve_clk@180";
		hdmi_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/hdmi_dpll_clk_mux@164";
		mlb_clk = "/ocp/l4@4ae00000/prm@6000/clocks/mlb_clk@134";
		mlbp_clk = "/ocp/l4@4ae00000/prm@6000/clocks/mlbp_clk@130";
		per_abe_x1_gfclk2_div = "/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_gfclk2_div@138";
		timer_sys_clk_div = "/ocp/l4@4ae00000/prm@6000/clocks/timer_sys_clk_div@144";
		video1_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/video1_dpll_clk_mux@168";
		video2_dpll_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/video2_dpll_clk_mux@16c";
		wkupaon_iclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/wkupaon_iclk_mux@108";
		gpio1_dbclk = "/ocp/l4@4ae00000/prm@6000/clocks/gpio1_dbclk@1838";
		dcan1_sys_clk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/dcan1_sys_clk_mux@1888";
		timer1_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/timer1_gfclk_mux@1840";
		uart10_gfclk_mux = "/ocp/l4@4ae00000/prm@6000/clocks/uart10_gfclk_mux@1880";
		prm_clockdomains = "/ocp/l4@4ae00000/prm@6000/clockdomains";
		scm_wkup = "/ocp/l4@4ae00000/scm_conf@c000";
		pcie1_rc = "/ocp/axi@0/pcie@51000000";
		pcie1_intc = "/ocp/axi@0/pcie@51000000/interrupt-controller";
		pcie1_ep = "/ocp/axi@0/pcie_ep@51000000";
		pcie2_rc = "/ocp/axi@1/pcie@51800000";
		pcie2_intc = "/ocp/axi@1/pcie@51800000/interrupt-controller";
		ocmcram1 = "/ocp/ocmcram@40300000";
		ocmcram2 = "/ocp/ocmcram@40400000";
		ocmcram3 = "/ocp/ocmcram@40500000";
		bandgap = "/ocp/bandgap@4a0021e0";
		dsp1_system = "/ocp/dsp_system@40d00000";
		dra7_iodelay_core = "/ocp/padconf@4844a000";
		mmc1_iodelay_ddr_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr_rev11_conf";
		mmc1_iodelay_ddr_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_ddr50_rev20_conf";
		mmc1_iodelay_sdr104_rev11_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev11_conf";
		mmc1_iodelay_sdr104_rev20_conf = "/ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev20_conf";
		mmc2_iodelay_hs200_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev11_conf";
		mmc2_iodelay_hs200_rev20_conf = "/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev20_conf";
		mmc2_iodelay_ddr_3_3v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_3_3v_rev11_conf";
		mmc2_iodelay_ddr_1_8v_rev11_conf = "/ocp/padconf@4844a000/mmc2_iodelay_ddr_1_8v_rev11_conf";
		mmc3_iodelay_manual1_rev11_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
		mmc3_iodelay_manual1_rev20_conf = "/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf";
		mmc4_iodelay_ds_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev11_conf";
		mmc4_iodelay_ds_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_ds_rev20_conf";
		mmc4_iodelay_sdr12_hs_sdr25_rev11_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev11_conf";
		mmc4_iodelay_sdr12_hs_sdr25_rev20_conf = "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev20_conf";
		sdma = "/ocp/dma-controller@4a056000";
		edma = "/ocp/edma@43300000";
		edma_tptc0 = "/ocp/tptc@43400000";
		edma_tptc1 = "/ocp/tptc@43500000";
		gpio1 = "/ocp/gpio@4ae10000";
		gpio2 = "/ocp/gpio@48055000";
		gpio3 = "/ocp/gpio@48057000";
		gpio4 = "/ocp/gpio@48059000";
		gpio5 = "/ocp/gpio@4805b000";
		gpio6 = "/ocp/gpio@4805d000";
		gpio7 = "/ocp/gpio@48051000";
		gpio8 = "/ocp/gpio@48053000";
		uart1 = "/ocp/serial@4806a000";
		uart2 = "/ocp/serial@4806c000";
		uart3 = "/ocp/serial@48020000";
		uart4 = "/ocp/serial@4806e000";
		uart5 = "/ocp/serial@48066000";
		uart6 = "/ocp/serial@48068000";
		uart7 = "/ocp/serial@48420000";
		uart8 = "/ocp/serial@48422000";
		uart9 = "/ocp/serial@48424000";
		uart10 = "/ocp/serial@4ae2b000";
		mailbox1 = "/ocp/mailbox@4a0f4000";
		mailbox2 = "/ocp/mailbox@4883a000";
		mailbox3 = "/ocp/mailbox@4883c000";
		mailbox4 = "/ocp/mailbox@4883e000";
		mailbox5 = "/ocp/mailbox@48840000";
		mbox_ipu1_ipc3x = "/ocp/mailbox@48840000/mbox_ipu1_ipc3x";
		mbox_dsp1_ipc3x = "/ocp/mailbox@48840000/mbox_dsp1_ipc3x";
		mailbox6 = "/ocp/mailbox@48842000";
		mbox_ipu2_ipc3x = "/ocp/mailbox@48842000/mbox_ipu2_ipc3x";
		mbox_dsp2_ipc3x = "/ocp/mailbox@48842000/mbox_dsp2_ipc3x";
		mailbox7 = "/ocp/mailbox@48844000";
		mailbox8 = "/ocp/mailbox@48846000";
		mailbox9 = "/ocp/mailbox@4885e000";
		mailbox10 = "/ocp/mailbox@48860000";
		mailbox11 = "/ocp/mailbox@48862000";
		mailbox12 = "/ocp/mailbox@48864000";
		mailbox13 = "/ocp/mailbox@48802000";
		timer1 = "/ocp/timer@4ae18000";
		timer2 = "/ocp/timer@48032000";
		timer3 = "/ocp/timer@48034000";
		timer4 = "/ocp/timer@48036000";
		timer5 = "/ocp/timer@48820000";
		timer6 = "/ocp/timer@48822000";
		timer7 = "/ocp/timer@48824000";
		timer8 = "/ocp/timer@48826000";
		timer9 = "/ocp/timer@4803e000";
		timer10 = "/ocp/timer@48086000";
		timer11 = "/ocp/timer@48088000";
		timer12 = "/ocp/timer@4ae20000";
		timer13 = "/ocp/timer@48828000";
		timer14 = "/ocp/timer@4882a000";
		timer15 = "/ocp/timer@4882c000";
		timer16 = "/ocp/timer@4882e000";
		wdt2 = "/ocp/wdt@4ae14000";
		hwspinlock = "/ocp/spinlock@4a0f6000";
		ipu1 = "/ocp/ipu@58820000";
		ipu2 = "/ocp/ipu@55020000";
		dsp1 = "/ocp/dsp@40800000";
		i2c1 = "/ocp/i2c@48070000";
		tps659038 = "/ocp/i2c@48070000/tps659038@58";
		smps12_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps12";
		smps3_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps3";
		smps45_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps45";
		smps6_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps6";
		smps8_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps8";
		ldo1_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo1";
		ldo2_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo2";
		ldo3_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo3";
		ldo4_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo4";
		ldo9_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo9";
		ldoln_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldoln";
		ldousb_reg = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldousb";
		regen1 = "/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/regen1";
		tps659038_rtc = "/ocp/i2c@48070000/tps659038@58/tps659038_rtc";
		tps659038_pwr_button = "/ocp/i2c@48070000/tps659038@58/tps659038_pwr_button";
		tps659038_gpio = "/ocp/i2c@48070000/tps659038@58/tps659038_gpio";
		extcon_usb2 = "/ocp/i2c@48070000/tps659038@58/tps659038_usb";
		tmp102 = "/ocp/i2c@48070000/tmp102@48";
		tlv320aic3104 = "/ocp/i2c@48070000/tlv320aic3104@18";
		eeprom = "/ocp/i2c@48070000/eeprom@50";
		i2c2 = "/ocp/i2c@48072000";
		i2c3 = "/ocp/i2c@48060000";
		mcp_rtc = "/ocp/i2c@48060000/rtc@6f";
		i2c4 = "/ocp/i2c@4807a000";
		i2c5 = "/ocp/i2c@4807c000";
		mmc1 = "/ocp/mmc@4809c000";
		mmc2 = "/ocp/mmc@480b4000";
		mmc3 = "/ocp/mmc@480ad000";
		mmc4 = "/ocp/mmc@480d1000";
		mmu0_dsp1 = "/ocp/mmu@40d01000";
		mmu1_dsp1 = "/ocp/mmu@40d02000";
		mmu_ipu1 = "/ocp/mmu@58882000";
		mmu_ipu2 = "/ocp/mmu@55082000";
		pruss_soc_bus1 = "/ocp/pruss_soc_bus@4b226004";
		pruss1 = "/ocp/pruss_soc_bus@4b226004/pruss@0";
		pruss1_mem = "/ocp/pruss_soc_bus@4b226004/pruss@0/memories@0";
		pruss1_cfg = "/ocp/pruss_soc_bus@4b226004/pruss@0/cfg@26000";
		pruss1_mii_rt = "/ocp/pruss_soc_bus@4b226004/pruss@0/mii_rt@32000";
		pruss1_intc = "/ocp/pruss_soc_bus@4b226004/pruss@0/intc@20000";
		pru1_0 = "/ocp/pruss_soc_bus@4b226004/pruss@0/pru@34000";
		pru1_1 = "/ocp/pruss_soc_bus@4b226004/pruss@0/pru@38000";
		pruss1_mdio = "/ocp/pruss_soc_bus@4b226004/pruss@0/mdio@32400";
		pruss_soc_bus2 = "/ocp/pruss_soc_bus@4b2a6004";
		pruss2 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0";
		pruss2_mem = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/memories@0";
		pruss2_cfg = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/cfg@26000";
		pruss2_iep = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/iep@2e000";
		pruss2_mii_rt = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/mii_rt@32000";
		pruss2_intc = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/intc@20000";
		pru2_0 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/pru@34000";
		pru2_1 = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/pru@38000";
		pruss2_mdio = "/ocp/pruss_soc_bus@4b2a6004/pruss@0/mdio@32400";
		abb_mpu = "/ocp/regulator-abb-mpu";
		abb_ivahd = "/ocp/regulator-abb-ivahd";
		abb_dspeve = "/ocp/regulator-abb-dspeve";
		abb_gpu = "/ocp/regulator-abb-gpu";
		mcspi1 = "/ocp/spi@48098000";
		mcspi2 = "/ocp/spi@4809a000";
		mcspi3 = "/ocp/spi@480b8000";
		mcspi4 = "/ocp/spi@480ba000";
		qspi = "/ocp/qspi@4b300000";
		sata_phy = "/ocp/ocp2scp@4a090000/phy@4A096000";
		pcie1_phy = "/ocp/ocp2scp@4a090000/pciephy@4a094000";
		pcie2_phy = "/ocp/ocp2scp@4a090000/pciephy@4a095000";
		sata = "/ocp/sata@4a141100";
		rtc = "/ocp/rtc@48838000";
		usb2_phy1 = "/ocp/ocp2scp@4a080000/phy@4a084000";
		usb2_phy2 = "/ocp/ocp2scp@4a080000/phy@4a085000";
		usb3_phy1 = "/ocp/ocp2scp@4a080000/phy@4a084400";
		omap_dwc3_1 = "/ocp/omap_dwc3_1@48880000";
		usb1 = "/ocp/omap_dwc3_1@48880000/usb@48890000";
		omap_dwc3_2 = "/ocp/omap_dwc3_2@488c0000";
		usb2 = "/ocp/omap_dwc3_2@488c0000/usb@488d0000";
		omap_dwc3_3 = "/ocp/omap_dwc3_3@48900000";
		usb3 = "/ocp/omap_dwc3_3@48900000/usb@48910000";
		elm = "/ocp/elm@48078000";
		gpmc = "/ocp/gpmc@50000000";
		atl = "/ocp/atl@4843c000";
		mcasp1 = "/ocp/mcasp@48460000";
		mcasp2 = "/ocp/mcasp@48464000";
		mcasp3 = "/ocp/mcasp@48468000";
		mcasp4 = "/ocp/mcasp@4846c000";
		mcasp5 = "/ocp/mcasp@48470000";
		mcasp6 = "/ocp/mcasp@48474000";
		mcasp7 = "/ocp/mcasp@48478000";
		mcasp8 = "/ocp/mcasp@4847c000";
		crossbar_mpu = "/ocp/crossbar@4a002a48";
		mac = "/ocp/ethernet@48484000";
		davinci_mdio = "/ocp/ethernet@48484000/mdio@48485000";
		phy0 = "/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@0";
		phy1 = "/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@2";
		cpsw_emac0 = "/ocp/ethernet@48484000/slave@48480200";
		cpsw_emac1 = "/ocp/ethernet@48484000/slave@48480300";
		phy_sel = "/ocp/ethernet@48484000/cpsw-phy-sel@4a002554";
		dcan1 = "/ocp/can@4ae3c000";
		dcan2 = "/ocp/can@48480000";
		gpu = "/ocp/gpu@56000000";
		bb2d = "/ocp/bb2d@59000000";
		dss = "/ocp/dss@58000000";
		hdmi = "/ocp/dss@58000000/encoder@58060000";
		hdmi_out = "/ocp/dss@58000000/encoder@58060000/port/endpoint";
		epwmss0 = "/ocp/epwmss@4843e000";
		ehrpwm0 = "/ocp/epwmss@4843e000/pwm@4843e200";
		ecap0 = "/ocp/epwmss@4843e000/ecap@4843e100";
		epwmss1 = "/ocp/epwmss@48440000";
		ehrpwm1 = "/ocp/epwmss@48440000/pwm@48440200";
		ecap1 = "/ocp/epwmss@48440000/ecap@48440100";
		epwmss2 = "/ocp/epwmss@48442000";
		ehrpwm2 = "/ocp/epwmss@48442000/pwm@48442200";
		ecap2 = "/ocp/epwmss@48442000/ecap@48442100";
		aes1 = "/ocp/aes@4b500000";
		aes2 = "/ocp/aes@4b700000";
		des = "/ocp/des@480a5000";
		sham = "/ocp/sham@53100000";
		rng = "/ocp/rng@48090000";
		opp_supply_mpu = "/ocp/opp-supply@4a003b20";
		vip1 = "/ocp/vip@0x48970000";
		vin1a = "/ocp/vip@0x48970000/port@0";
		vin2a = "/ocp/vip@0x48970000/port@1";
		vin1b = "/ocp/vip@0x48970000/port@2";
		vin2b = "/ocp/vip@0x48970000/port@3";
		dsp2_system = "/ocp/dsp_system@41500000";
		omap_dwc3_4 = "/ocp/omap_dwc3_4@48940000";
		usb4 = "/ocp/omap_dwc3_4@48940000/usb@48950000";
		mmu0_dsp2 = "/ocp/mmu@41501000";
		mmu1_dsp2 = "/ocp/mmu@41502000";
		dsp2 = "/ocp/dsp@41000000";
		vip2 = "/ocp/vip@0x48990000";
		vin3a = "/ocp/vip@0x48990000/port@0";
		vin4a = "/ocp/vip@0x48990000/port@1";
		vin3b = "/ocp/vip@0x48990000/port@2";
		vin4b = "/ocp/vip@0x48990000/port@3";
		vip3 = "/ocp/vip@0x489b0000";
		vin5a = "/ocp/vip@0x489b0000/port@0";
		vin6a = "/ocp/vip@0x489b0000/port@1";
		thermal_zones = "/thermal-zones";
		cpu_thermal = "/thermal-zones/cpu_thermal";
		cpu_trips = "/thermal-zones/cpu_thermal/trips";
		cpu_alert0 = "/thermal-zones/cpu_thermal/trips/cpu_alert";
		cpu_crit = "/thermal-zones/cpu_thermal/trips/cpu_crit";
		cpu_alert1 = "/thermal-zones/cpu_thermal/trips/cpu_alert1";
		cpu_cooling_maps = "/thermal-zones/cpu_thermal/cooling-maps";
		gpu_thermal = "/thermal-zones/gpu_thermal";
		gpu_crit = "/thermal-zones/gpu_thermal/trips/gpu_crit";
		core_thermal = "/thermal-zones/core_thermal";
		core_crit = "/thermal-zones/core_thermal/trips/core_crit";
		dspeve_thermal = "/thermal-zones/dspeve_thermal";
		dspeve_crit = "/thermal-zones/dspeve_thermal/trips/dspeve_crit";
		iva_thermal = "/thermal-zones/iva_thermal";
		iva_crit = "/thermal-zones/iva_thermal/trips/iva_crit";
		board_thermal = "/thermal-zones/board_thermal";
		board_trips = "/thermal-zones/board_thermal/trips";
		board_alert0 = "/thermal-zones/board_thermal/trips/board_alert";
		board_crit = "/thermal-zones/board_thermal/trips/board_crit";
		board_cooling_maps = "/thermal-zones/board_thermal/cooling-maps";
		ipu2_memory_region = "/reserved-memory/ipu2-memory@95800000";
		dsp1_memory_region = "/reserved-memory/dsp1-memory@99000000";
		ipu1_memory_region = "/reserved-memory/ipu1-memory@9d000000";
		dsp2_memory_region = "/reserved-memory/dsp2-memory@9f000000";
		cmem_block_mem_0 = "/reserved-memory/cmem_block_mem@a0000000";
		cmem_block_mem_1_ocmc3 = "/reserved-memory/cmem_block_mem@40500000";
		main_12v0 = "/fixedregulator-main_12v0";
		evm_5v0 = "/fixedregulator-evm_5v0";
		vdd_3v3 = "/fixedregulator-vdd_3v3";
		aic_dvdd = "/fixedregulator-aic_dvdd";
		vtt_fixed = "/fixedregulator-vtt";
		gpio_fan = "/gpio_fan";
		hdmi0 = "/connector";
		hdmi_connector_in = "/connector/port/endpoint";
		tpd12s015 = "/encoder";
		tpd12s015_in = "/encoder/ports/port@0/endpoint";
		tpd12s015_out = "/encoder/ports/port@1/endpoint";
		sound0 = "/sound0";
		sound0_master = "/sound0/simple-audio-card,codec";
		cmem_block_0 = "/cmem/cmem_block@0";
		cmem_block_1 = "/cmem/cmem_block@1";
	};
};

Is there another variants to solve this issue?

I am grateful for your help!

Anton,

Driver seems to be looking for the vqmmc-supply.

File: drivers/mmc/host/sdhci-omap.c

sdhci_omap_probe --> sdhci_omap_set_capabilities

        vqmmc = regulator_get(dev, "vqmmc");
        if (IS_ERR(vqmmc)) {
                ret = PTR_ERR(vqmmc);
                goto reg_put;
        }

Do you know which regulator is supplying that on your board?
If it is not modeled then try bypassing that check.

- Keerthy

Keerthy J, on my board I have not regulator like pmic.

I bypassed check in driver:

static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
{
	u32 reg;
	int ret = 0;
	struct device *dev = omap_host->dev;
	struct regulator *vqmmc;

	vqmmc = regulator_get(dev, "vqmmc");
	/*if (IS_ERR(vqmmc)) {
		ret = PTR_ERR(vqmmc);
		goto reg_put;
	}*/

	/* voltage capabilities might be set by boot loader, clear it */
	reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA);
	reg &= ~(CAPA_VS18 | CAPA_VS30 | CAPA_VS33);

	if (regulator_is_supported_voltage(vqmmc, IOV_3V3, IOV_3V3))
		reg |= CAPA_VS33;
	if (regulator_is_supported_voltage(vqmmc, IOV_1V8, IOV_1V8))
		reg |= CAPA_VS18;

	sdhci_omap_writel(omap_host, SDHCI_OMAP_CAPA, reg);

reg_put:
	regulator_put(vqmmc);

	return ret;
}

Output changed but boot still stopped:

....
[    3.821932] vdd_3v3: disabling
[    3.821936] aic_dvdd_fixed: disabling
[    3.821944] pbias_mmc_omap5: disabling
[    3.821955] ALSA device list:
[    3.821958]   No soundcards found.
[    3.848054] of_get_named_gpiod_flags: can't parse 'hpd-gpios' property of node '/connector[0]'
[   3.856798] connector-hdmi connector: failed to find video source
[    3.863163] panel-dpi display: GPIO lookup for consumer enable
[    3.869024] panel-dpi display: using device tree for GPIO lookup
[    3.875098] of_get_named_gpiod_flags: parsed 'enable-gpios' property of node '/display[0]' - status (0)
[    3.884559] panel-dpi display: GPIO lookup for consumer reset
[    3.890345] panel-dpi display: using device tree for GPIO lookup
[    3.896382] of_get_named_gpiod_flags: can't parse 'reset-gpios' property of node '/display[0]'
[    3.905048] of_get_named_gpiod_flags: can't parse 'reset-gpio' property of node '/display[0]'
[    3.913629] panel-dpi display: using lookup tables for GPIO lookup
[    3.919852] panel-dpi display: lookup for GPIO reset failed
[    3.925465] panel-dpi display: display supply vcc not found, using dummy regulator
[    3.933193] panel-dpi display: failed to find video source
[    3.940124] sdhci-omap 4809c000.mmc: GPIO lookup for consumer cd
[    3.946160] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.952742] of_get_named_gpiod_flags: can't parse 'cd-gpios' property of node '/ocp/mmc@4809c000[0]'
[    3.961936] of_get_named_gpiod_flags: can't parse 'cd-gpio' property of node '/ocp/mmc@4809c000[0]'
[    3.971044] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    3.977776] sdhci-omap 4809c000.mmc: lookup for GPIO cd failed
[    3.983656] sdhci-omap 4809c000.mmc: GPIO lookup for consumer wp
[    3.989706] sdhci-omap 4809c000.mmc: using device tree for GPIO lookup
[    3.996264] of_get_named_gpiod_flags: can't parse 'wp-gpios' property of node '/ocp/mmc@4809c000[0]'
[    4.005456] of_get_named_gpiod_flags: can't parse 'wp-gpio' property of node '/ocp/mmc@4809c000[0]'
[    4.014557] sdhci-omap 4809c000.mmc: using lookup tables for GPIO lookup
[    4.021302] sdhci-omap 4809c000.mmc: lookup for GPIO wp failed
[    4.027314] sdhci-omap 4809c000.mmc: 4809c000.mmc supply vqmmc not found, using dummy regulator
[    4.036563] Waiting for root device PARTUUID=a464469c-02...

Hi, Keerthy J.

Also I see that ret = sdhci_setup_host(host); in sdhci-omap.c return -EPROBE_DEFER

Stack sdhci_setup_host() -> mmc_regulator_get_supply() return -EPROBE_DEFER in code:

if (IS_ERR(mmc->supply.vmmc)) {
	if (PTR_ERR(mmc->supply.vmmc) == -EPROBE_DEFER) {
		return -EPROBE_DEFER;
	}
	dev_dbg(dev, "No vmmc regulator found\n");
}

Is this normal?

Hi Anton,

So vmmc-supply = <0xcf>; is what i am seeing in your DTS.

fixedregulator-vdd_3v3 {
compatible = "regulator-fixed";
regulator-name = "vdd_3v3";
vin-supply = <0x127>;
regulator-min-microvolt = <0x325aa0>;
regulator-max-microvolt = <0x325aa0>;
phandle = <0xcf>;
};

Is also present. Why is this failing & returning -EPROBE_DEFER?

- Keerthy