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C6A8168 Switched Central Resource (SCR) bandwidth

TommyG
Genius 13045 points

I would like to know if there is any information available on the bandwidth of the SCR shown in the block diagram shown at the top of the Product Folder.  I think this is the same as Bus Interconnect discussed in the TRM (SPRUGX9, sec 1.11).  I would like to understand how many Initiators and Targets can be active at the same time and what is the total bandwidth of the SCR.  This will help me understand where potential bottlenecks are going to occur in different applications.  In the past the on chip interconnect has been one of the bottlenecks in data flow through a system.  I want to understand how this has improved with the new devices.

Thanks.

  • 0
    TI__Mastermind 25055 points

    Hi,

    Yes, it refers to the L3 and L4 interconnects, as shown in the Datasheet and in the TRM.  The figure in the TRM shows the bandwidth for the initiator and targets ports on the interconnect.  The L4 can handle incoming traffic from up to four initiators and can distribute those communication requests to and collect related responses from up to
    63 targets.

    Regards,
    Marc