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OMAP-L138: Interrupts to Both CPU's

Benjamin Michaud
Expert 1825 points
Part Number: OMAP-L138


Hi,

This is a two part question.

1.  We currently have our schematic setup using the OMAP-L138 and need to use external interrupts with both CPU's.

Essentially on port 1 pin 1 we will need an interrupt to be triggered for the ARM CPU, and on the same port pin 2 we will need to trigger an interrupt for the DSP.

Is it possible to setup the OMAP-L138 to trigger interrupts for both CPU's on the same port?

2.  In our design both the ARM and DSP will need to access external devices over the external memory interface.

I seem to remember reading that when a hardware resource is shared between the two CPU's, it is done so on a first come first serve basis (no CPU starvation this way).

Is that the case, or is there a difference policy for sharing the external memory interface between the CPU's?

Thanks,

Ben

  • 0
    TI__Guru** 116320 points
    Benjamin Michaud said:

    1.  We currently have our schematic setup using the OMAP-L138 and need to use external interrupts with both CPU's.

    Essentially on port 1 pin 1 we will need an interrupt to be triggered for the ARM CPU, and on the same port pin 2 we will need to trigger an interrupt for the DSP.

    Is it possible to setup the OMAP-L138 to trigger interrupts for both CPU's on the same port?

    This should be possible. Both the ARM and DSP have their own Interrupt controller so you can route the interrupts independently to the DSP and ARM. 

    Benjamin Michaud said:

    2.  In our design both the ARM and DSP will need to access external devices over the external memory interface.

    I seem to remember reading that when a hardware resource is shared between the two CPU's, it is done so on a first come first serve basis (no CPU starvation this way).

    Your understanding is correct if you are referring to EMIFB interface which connects to DDR memory. Generally this is the policy enabled by default. OS based shared memory implementations may implement gates, mutex, semaphores to synchronize access to external memory and to prevent memory corruption due to simultaneous access.

  • 0 in reply to Rahul Prabhu
    Expert 1825 points

    Hi Rahul,

    I am testing out question 1 on the OMAP-L138 LCDK evaluation board.

    Both S2 and S3 go to the same port on the OMAP-L138.

    I was able to successfully setup interrupt handlers for both buttons with the ARM or DSP.

    However, when I try to get 1 button triggering an interrupt on the ARM, and the other button triggering an interrupt on the DSP it does not work.

    Only the first CPU to initialize the I/O's and interrupt handler will service the interrupt when its button is pushed.

    The second CPU to initialize the I/O's and interrupt handler will never service the interrupt when its button is pushed.

    Does TI have any example code showing how to initialize different ISR's with different CPU's, but on the same I/O port?

    Since the code for both CPU's work if they are the first to run I don't think I have necessarily configured the interrupts incorrectly, and it might be more me needing to learn how to use the GPIO library or something else.

    Ben