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OMAP L138 DDR2 RAM Check

Wes Hubbell
Prodigy 80 points

Hello,

We have a requirement to check RAM - as fast as possible - (cache disabled).

The RAM check must check the entire RAM and perform the following:

1. Fill entire RAM with pattern 1 (ie: 55h)

2. Read/verify pattern 1 while writing pattern 2 (ie: AAh)

3. Read/verify pattern 2 while writing pattern 3 (ie: FFh)

4. Read/verify pattern 3 while writing pattern 4 (ie: 0)

5. Read/verify pattern 4.

Question: What is the fastest way to do this and how long would it take to for say a 256MB RAM (assume RAM is faster than OMAP processor (ie: faster than 300 MHz)).

Without fully knowing all the methods available to do this we started with an approach that makes 32 bit reads and writes using the ARM. first pass we estimate 27 seconds. (Compiler generated assy code roughly 123 cycles X 256M/4 X 1/cpu speed (cpu speed = 300 MHz).

However - there may be faster ways to do this - any ideas?

Thank you

wes

  • 0
    TI__Mastermind 27585 points

    The fastest way would be to use the EDMA rather than CPU reads.

    To estimate the time, can you explain what happens in steps 2-4 in more detail? When you say "while" does that mean you are reading, verifying, and overwriting one word at a time? Wouldn't it be more efficient to do these as separate steps, or is that a requirement for your tests?

    Jeff

  • 0 in reply to jc-ti
    Prodigy 80 points

    Thank you for replying Jeff. The "while" was from a previous processor that had the ability (as in a command) to read content and then write content with one step. We do not have a requirement to do it one step and it could be done in separate steps.

    Clarification/explanation of steps 2-4: all we are trying to do is read back what was written in previous step and make sure it matches - when that is done we write the next pattern. our requirement is to do this for 4 patterns (all 1's, 01's, 10's, all 0's). Note - we must write each pattern to the entire RAM (to test it).

    Since we are new to the OMAP and its EDMA - am unsure on estimating the time - so any help or insight is much appreciated! Thank you

    wes

  • 0 in reply to Wes Hubbell
    TI__Mastermind 27585 points

    If EDMA is used for the writes, you can expect around 90% throughput. With a DDR2 clock of 150MHz, your data write rate would be 256MB / (300MHz * 2B * 90%) = 0.47 seconds to fill the entire memory.

    The readback and verify portion would depend on the methods used. The DSP is capable of doing 64-bit double load/stores, while the ARM can only do 32-bit load/stores, so you would get better performance using the DSP rather than the ARM.

    In addition, you should enable the cache for the readbacks, as this will perform burst reads rather than single accesses. You can invalidate the cache before you begin your readback to make sure every access is fetching externally.

    Jeff

  • 0 in reply to jc-ti
    Prodigy 80 points

    Very good - so it takes half a second to write one pattern to the entire with the EDMA. We like the idea of using the DSP - and we are required to disable cache (during entire RAM check - although we could see if it is possible to use it for readback but lets assume no cache for now)

    So granted we can use the DSP but we don't have cache enabled for readbacks - how long do you think it would take to do the readback and check for one pattern that filled the entire 256MB RAM?

    Thank you

    wes

  • 0 in reply to Wes Hubbell
    TI__Mastermind 27585 points

    I think the best way to find this would be to just test it out.

    With the cache enabled, you might expect the readback and verify to drop your throughput to around 60% of the DDR theoretical maximum. However without the cache it will be slower than this since it will not prefetch additional data for each read.

    Jeff