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66AK2G12: Keystone 2power up/down sequence

Avner Cohen
Intellectual 460 points
Part Number: 66AK2G12

Hi I am designing my board with the Ti SOC 66ak2g12
The datasheet states that the SOC power up sequence is as this order (using figure 5-3) :
3.3V (DVDD33) then 1.8V,1.0V DDR and Core voltage.

The Artix family of FPGA by Xilinx requires the opposite sequence first FPGA core1.0V,  then 1.8V_AUX and lastly the 3.3V I/O.

  • I see two options that can be to power on the SOC+  FPGA :
    1. 0VFPGAcore ->1.8V FPGA_Aux -> 3.3VFPGA and_SOC_IO -> 1.8VDDR+1.0VSOC_core
    2. 3V_SOC_IO(only) -> 1.8VDDRand FPGA_AUX+1.0V_SOC_core ->3.3V FPGA_IO(only)

Both option have possibility of leakage voltage that will cause the power up to be from certain voltage and not from 0V. (for example the in B, before turning on the FPGA 3.3V IO the FPGA will have ~~2.3V.

Similarly in option a I fear that the SOC might have leakage voltage on the 1.8V and core voltage before turning them on. (That leakage will come from the FPGA IOs connected to SOC)

Please advise  at what order do you recommend to perform the power up/ down sequence ? and your comments on the above.

 

  • Do you have application note or evaluation board combining the two SOC (Keystone2 and Artix FPGA ) ?
  • Please take a look at Ti’s article on power sequence :

Sequencing and managing multiple power rails in a system: common questions answered - Power management - Technical articles - TI E2E support forums

At what type of implementation the SOC power should be ? sequential , radiometric or simultaneous ?

  • If I use simple voltage monitor that causes reset when power is down. Meaning the requirement of resetting the SOC before the power is down, is kept, what is the importance of the power down ? meaning if the power down sequence is not kept what will happen. Remember that the power down period is of few milliseconds.

 

Thanks

  Avner

  • 0
    TI__Guru 63125 points

    Power sequencing is a system level concern where the designer must understand limitations of all on-board and all off-board attached devices. 66AK2G12 requires the 3.3V supplies to be turned on before any of the other supplies, but there is no specific requirement associated with sequencing of the other supplies.

    I assume a few 66AK2G12 IOs will be connected to FPGA IOs. If so, the respective IOs of each device should be powered from a common IO supply. A common supply is necessary because the 66AK2G12 IOs are not fail-safe and I suspect the same is true for the FPGA IOs. Sourcing the IOs with a common power supply eliminates the risk of one IO sourcing a potential to the attached IO before it receives power.

    If the above is true, I feel your option #1 would be best for your system. However, this prevents you from sharing a 1.0V and 1.8V power rail with 66AK2G12 and FPGA since one must be sequenced on/off before the other. This will require separate 1.0V and 1.8V supplies for 66AK2G12 and FPGA.

    You mention option B and option A in your description. I assume option A is the same as #1 and option B is the same as #2. If so, I agree option B would be problematic as the IOs of 66AK2G12 is likely sourcing a potential to the FPGA IOs before it is powered and current will flowing through the ESD protection circuit of each FPGA IO to the FPGA IO power rail. This condition may cause a long-term reliability issue for the FPGA.

    I do not understand your concern with option A (#1) as long as you provide separate supplies for the 66AK2G12 and FPGA 1.0V and 1.8V power rails.

    You will need to make sure there are no other devices in your system that cross a voltage domain and cause a problem.

    I’m not aware of an application note that addresses these concerns as they are very system implementation dependent.

    The power sequencing recommendation for 66AK2G12 is sequential with respect to the 3.3V supply turning on before any of the other supplies.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 460 points

    Thanks Paul for the answer.

     

    I will go for option 1 and make sure there will be no voltage that will cross the 1.8V domain of the FPGA and the 1.8V of the SOC/DDR 1.8V

    Can you please refer to my question on the power down ?

    The reset and the actual remaining voltages sequence before they become 0V

    Also if you aware of evaluation board schematics, that combines the Xilinx Artix FPGA and the SOC keystone2 or similar one?

     

    Another question regarding the SYSOSC clock and power sequence please:

    From reliability and temperature reasons I use external 25Mhz clock attached to the SYSOSC_IN. the oscillator is powered from the 1.8V which its sequence is after the 3.3V and together with DVDD18.

    That means no clock at the time the 3.3 of the SOC when it is going up and it will be valid only when the DVDD18 is up and before Vcore is up.

    I will make sure the reset pin POR will rise some at least 2 mS after the whole power and clock are stable. Do you think that is right design or has flaw ?

    There is a note on page 99  :

    “When connecting SYSOSC_IN to an LVCMOS clock source, the LVCMOS clock source

    output must be disabled anytime SYSOSC is disabled since SYSOSC_IN has a strong

    internal pull-down resistor which is turned on when SYSOSC is disabled”

     

     Q: when and how the SYSOSC is disabled ? does it relates to power down sequence ?

    Can you please recommend how to connect the oscillator +its enable +power to SYSOSC_IN ?

     

    Thanks

      Avner

  • 0 in reply to Avner Cohen
    TI__Guru 63125 points

    I'm not sure what you are asking about the power-down sequence. The 66AK2G12 datasheet provides a recommended power down-sequence, where the supplies are expected to turn off in reverse order of the power on sequence. I'm not sure how this sequence aligns with other devices in your system. This is something you will need to account for in your system design.

    I'm not familiar with the Xilinx Artix FPGA family of devices or aware of any hardware evaluation platforms that include both devices.

    I would not expect an issue sequencing power to the LVCMOS clock source at the same time as the 66AK2G12 DVDD18 power rail. Actually this is what we expect you to do. This will be equivalent to using the crystal circuit, as the device does not receive a reference clock until 1.8V power is applied even when using a crystal circuit. 

    You should be good as long as you assert reset until all power supplies and clocks are valid.

    SYSOSC is enabled by default and should remain enabled unless you specifically disable it by writing to a register. AUDOSC is disabled by default. This is why any external source connected to it must also be disabled by default. 

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 460 points

    Hi Paul,

    Thanks for the quick response !

    Regarding the power down I would like to know the effect :

    If the POR will be active and cause the SOC to be in reset state. What will happen if the 3.3V will go down before the 1.8V or the core 1.0V ?

    That violation will be for few milliseconds.

    Since the SOC is in reset, there is no fear of CPU to enter unknown state, or software to go garbage, so will it cause damage in short/long time ?

    What will be the effect of not powering down in reverse order, as long as  I reset prior to power down ?

     

    Thanks

      Avner

  • 0 in reply to Avner Cohen
    TI__Guru 63125 points

    There is no way to be sure the SOC is held in reset once the 3.3V power is turned off since the PORn input buffer is powered from the 3.3V power rail. 

    There was no plan to support 3.3V being turned off first, so this condition was not considered or evaluated. Therefore, we do not know what will happen or if you will experience any long-term reliability issues when not following the recommended power-down sequence.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 460 points

    Hi Paul,

    I think you can say the same for the scenario of going as recommended power down.

    If the POR is active resetting the SOC and the 1.0V core and the 1.8V are down and the 3.3V is still up,  you cannot be sure that the SOC is in reset, nor that it will not  run wrongly.

    The other chip vendors saying that excessive current will be drawn when violating the power up/down sequence, and damage will not occur thus it is not so significant on power down. (for violation period of few milliseconds)

    But here I am being required to withstand the power down.

    In any case, I think I got the most.

    Appreciate your help.

    Thanks

      Avner

  • 0 in reply to Avner Cohen
    TI__Guru 63125 points

    I'm more familiar with design details of our processors that contain dual-voltage IOs, where there is a 1.8V bias supply for all IOs. For those devices, the 1.8V IO bias supply is required to be first to power-up and last off to power-down. There is a IO reset signal generated within this 1.8V bias supply that connects to all IOs and holds them in a know state while the core is not powered. This prevents the core logic from sourcing unexpected signals to IOs as the core supply ramps up/down. I suspect there is a similar reset implemented in this device, except it is in the 3.3V domain. This allows reset to control the IOs while the core is not powered. Therefore, our power-up and power-down sequence requirements are primarily trying to protect attached devices. For example, most of our IOs are implemented with bi-directional IO cells and we would not want the core circuits to accidently force the output driver on when connected to another device driving a signal to a different logic level.

    Regards,
    Paul