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AM3352: LCD Controller, Raster controller Vsync and HSync timing

Junpei Kishi
Intellectual 865 points
Part Number: AM3352

Hi team,

Figure13-27 in TRM shows VSYNC rising edges sync with HSYNC rising edges.
However, in our board, VSYNC falling edges sync with HSYNC rising edges. (We set invert flag for both VSYNC and HSYNC)

How can I align VSYNC falling edges to HSYNC falling edges? 

Best Regards,
Junpei Kishi

  • +1
    TI__Expert 3300 points

    Hi Junpei,

    The LCD controller does not support aligning edges of VSYNC and HSYNC pulses. 

    One solution that was previously suggested was to only invert HSYNC, that way, the LCD display sees that the edges are aligned. This would result in an HSYNC "pulse" that is the entire length of the horizontal line (minus the HSYNC width), so that may also be an issue for the LCD display. 

    Another potential "solution" that should allow your LCD to display the correct image (but won't change this timing relationship) is to change RASTER_TIMING_0/1 registers such that the data is slightly shifted, so increase your vertical back porch for example while simultaneously decreasing your front porch (by as little as 1) :

    VBP = VBP + x

    VFP = VFP - x

    And generally change these values until you get the expected image. 

    Best,

    Andrei

  • 0 in reply to Andrei Aldea
    TI__Intellectual 865 points

    Hi Andrei,

    Thank you for your reply.
    But, could you let me know about additional questions listed below?

    1. I wonder what the mean of Figure 13-27 in AM335x TRM shows something "sync" between VSYNC and HSYNC.
    2. Is the gap between VSYNC fall edge and HSYNC fall edge variable? Or, the gap is fixed while the processor is running?
    3. We are using a LCD which require the timing showed below.
      It requests syncing between the fall edges of HSYNC and VSYNC.
      I understood that AM3352 cannot output following this chart, is it right? 

    Best Regards,
    Junpei Kishi

  • +1 in reply to Junpei Kishi
    TI__Expert 3300 points

    Hi Junpei,

    Sure thing. To answer your questions in order:

    1. I'm not sure what you mean by this, can you elaborate? 

    2. The gap is fixed while the processor is running depending on the timing parameters you set the LCDC to. 

    3. AM335 cannot output a signal where both VSYNC and HSYNC fall on the exact same clock edge, no. They will always have some delay between that two. Most displays do however have some leeway in how this timing is implemented.

    Best Regards,

    Andrei

  • 0 in reply to Andrei Aldea
    TI__Intellectual 865 points

    Hello Andrei,

    I understood about #2,3.
    Thanks a lot for quick response!

    > #1
    I mean, the figure on TRM seems to show that the rising edges of VSync and HSync are aligned. (at the first pulse of HSync)

    Regards,
    Junpei

  • 0 in reply to Junpei Kishi
    TI__Expert 3300 points

    That seems to be a case where the illustrator wanted to represent a generic use case and  did not consider that it would be read this way. I will have our team review this and consider adjusting it. 

    Best,

    Andrei

  • 0 in reply to Andrei Aldea
    TI__Intellectual 865 points

    Ok, I got it.
    Anyway, thank you for all your help!

    Best Regards,
    Junpei

  • 0 in reply to Junpei Kishi
    TI__Expert 3300 points

    Anytime, glad to be of help!