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dm3730 arm privilize mode issue

sri nidhi
Prodigy 140 points
Other Parts Discussed in Thread: DM3730

Hello All,

I am facing a problem with privilize mode of dm3730 processor in dm3730 evm.
  The problem is that the dpll(0th bit of CM_IDLEST_PLL_MPU register of MPU_CM Register set)
  is not locking in privilize mode of the arm,but it is locking in the user mode,what can be the reason for the problem ?
  can we not lock the dpll in privilize mode? am i missing any intialization sequence or register setting in privilize mode?

same the case with CM_AUTOIDLE_PLL_IVA2 register of IVA2_CM Register set i.e. locking in the user mode but not locking in the previlize mode of arm.what can

be the reason?

Thanks in advance,


Best Trgards,
Nidhi

 

 

 

  • 0
    TI__Guru* 84110 points

    Nidhi,

    I hope you have solved your problem by now. It is sad that no one has responded in this amount of time, but that may just mean that no one can figure out why you have this problem.

    My assumption is that "privilize" means "privilege". I also assume that you mean the ST_MPU_CLK bit is not set in the CM_IDLEST_PLL_MPU register when the ARM is running in "supervisor" mode but that it is set when the ARM is running in "user" mode. Are all of these assumptions correct.

    There is no reason that I can think of why you should get this behavior. If you have done additional debug and determined the cause of your problem, please post it here so the next person searching for this problem will gain from your experience.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Prodigy 140 points

    Thanks for the reply RandyP,

    Still I am not able to figure out the reason for the Problem,on which I am still working.

    All of your assumptions are currect.

    Once If i get the solution for my problem,definitely I will post  that solution.

     

    Best Regards,

    E.B.Srinidhi