Other Parts Discussed in Thread: TDA4VM,
Hello,
I'm trying to debug with CCS 10.2 on the Jacinto processor. I use the J721E RTOS-SDK version 07.03.00.07 under Windows 10.
So far, debugging worked well on the EVM with the TDA4VM.
Now we have our own custom board with the DRA829V instead of the TDA4VM, and with a different DDR-SDRAM (we use MT53E256M32D2, EVM has MT53D1024M32D4DT, both from Micron).
When I try to debug on our custom board, the CCS debug script stops during DDR configuration with the following output:
Java script console output:
js:> loadJSFile("J:/ti/drv/sciclient/tools/ccsLoadDmsc/j721e/launch.js")Connecting to DMSC_Cortex_M3_0!Fill R5F ATCM memory...Writing While(1) for R5FLoading DMSC Firmware ... J:/ti/drv/sciclient/soc/sysfw/binaries/ti-fs-firmware-j721e-gp.binDMSC Firmware Load Done...DMSC Firmware run starting now...Connecting to MCU Cortex_R5_0! WKUP Boot Mode is 56 Main Boot Mode is 17Running the board configuration initialization from R5!Running the DDR configuration... Wait till it completes!Error evaluating "J7ES_LPDDR4_Config_Late()": Timed out after 200000ms (J:\ti\drv\sciclient\tools\ccsLoadDmsc\j721e\launch.js#157)js:>
GEL console output:
[...]
DMSC_Cortex_M3_0: GEL Output: Powering up all PSC power domains done!
DMSC_Cortex_M3_0: GEL Output: Configuring drive strength.
DMSC_Cortex_M3_0: GEL Output: First, unlock the MMRs.
DMSC_Cortex_M3_0: GEL Output: Unlocked MMRs.
DMSC_Cortex_M3_0: GEL Output: Configuring horizontal drive strength.
DMSC_Cortex_M3_0: GEL Output: Horizontal drive strength configured.
DMSC_Cortex_M3_0: GEL Output: Configuring vertical drive strength.
DMSC_Cortex_M3_0: GEL Output: Vertical drive strength configured.
DMSC_Cortex_M3_0: GEL Output: LVCMOS drive strength configured to 0xD
DMSC_Cortex_M3_0: GEL Output: --->>> LPDDR4 Initialization is in progress ... <<<---
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)
DMSC_Cortex_M3_0: GEL Output: Set PLL to external bypass (20MHz/19.2MHz on SVB/EVM).
DMSC_Cortex_M3_0: GEL Output: --->>> DDR controller programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR controller programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 0 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 0 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 1 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 1 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 2 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 2 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 3 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Data Slice 3 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Address slice 0 programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY Address Slice 0 programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY programming in progress.. <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PHY programming completed... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR PI initialization started... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> DDR Controller initialization started... <<<---
DMSC_Cortex_M3_0: GEL Output: --->>> Waiting for frequency change requests ... <<<---
DMSC_Cortex_M3_0: GEL Output: Frequency change request type 1 received from controller
DMSC_Cortex_M3_0: GEL Output: Setting DDR PLL + HSDIV to 933MHz
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x80170000
DMSC_Cortex_M3_0: GEL Output: DDR PLL Calibration Control MMR value: 0x800001CA
DMSC_Cortex_M3_0: GEL Output: DDR PLL + HSDIV set to 933MHz.
Until this point, the GEL output is the same on our board and on the EVM. On our custom board, the output stops here, while on the EVM, several more "Frequency Change Requests" occur before the initialization is completed successfully.
Because of the different memory device, I downloaded the DDRSS config tool (Jacinto7_DDRSS_RegConfigTool.xlsm) and checked all parameters against the data sheet. Some where slightly different, leading to a different GEL DDRSS config file. However, the behavior is still the same. I also tried different DDR memory frequencies. I could see that the PLL is then set to a different frequency (so the generated config was definitely used), but the error persists.
When I look at the GEL script, it seems it is waiting for another Frequency Change Request issued by the DDRSS, which never comes.
Any ideas what could be the root cause here? Maybe there are any status bits to see why the DDRSS does not issue any more request? Or might this be caused by a difference between DRA829V and TDA4VM?
By the way, when I disable the DDRSS initialization in the debugger scripts, an application linked to the internal RAM can be loaded and runs properly, so it doesn't look like a general problem with debugging or with the processor on our custom board.
Regards
Thomas
