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TDA4VM: TDA4VM OSPI communication with Flash memory timing spec questions

TAEHYUN KIM
Prodigy 210 points
Part Number: TDA4VM

Hello. 

I have some basic questions about OSPI communication with Flash memory.

currently i use a flash memory with DDR and OSPI mode for booting.

Could you please explain below the questions?

1. What exactly DQS(data strobe) do?

- Is DQS a signal to synchronize with DQ in READ mode?

- or Is DQS a signal to capture DQ when DQS goes to HIGH or LOW in READ mode?

- Does DQS not use in WRITE mode?

2. How can i distinguish between READ mode and WRITE mode by signals(CS, CLK, DQ, DQS) ?

3. I want to check the OSPI interface about timing specifications(CS, CLK, DQ, DQS) between SoC and DDR OSPI Flash.

- for READ mode , Timing requirements (CS, CLK, DQ, DQS correlation) 

- for WRITE mode , Timing specifications (CS, CLK, DQ, DQS correlation) 

4. Please explain the specific method and process of 7.10.5.21.1 OSPI with Data training.

Thank you for your help.

  • 0
    Intellectual 270 points

    Hello,

    the same question regarding QSPI timing required popped also up here in our project. Can anyone from TI please give some additional information? The information in the TDA4VM data sheet for the OSPI interface timing is not detailed enough.

  • 0 in reply to Thomas Dedler
    TI__Expert 4015 points

    1. What exactly DQS(data strobe) do?
    DQS is used to capture data. It captures data on the rising edge in the case of SDR mode, and on both edges in the case of DDR mode. It is not used in write transactions.

    2. How can i distinguish between READ mode and WRITE mode by signals(CS, CLK, DQ, DQS) ?
    Assuming that all of your read transactions are using DQS, then CS, CLK, and DQ will be the same for READ and WRITE, but DQS will toggle only during READ transactions.

    3. I want to check the OSPI interface about timing specifications(CS, CLK, DQ, DQS) between SoC and DDR OSPI Flash.
    For WRITE transactions, see the switching characteristics tables for DDR and SDR modes.
    DQS -not used.
    Clock to Data delay - O6 (DDR) and O12 (SDR)
    Clock to CS delay - O4/O5 (DDR) and O10/O11 (SDR)

    For Read transactions, switching characteristics apply during the address write phase of the transaction. Additionally, the timing requirements table contains the clock to data relationships (setup and hold times) that must be met.

    4. Please explain the specific method and process of 7.10.5.21.1 OSPI with Data training.
    Here is an application note with details.
    www.ti.com/.../spract2.pdf

    The above applies to QSPI as well as OSPI.