multi master support for i2c on J5-Eco, J6

Josmon Paul

We have a requirement to access i2c bus from M core( Autosar )and A core (Linux) . So this is a multimaster scenario for i2c. Does J6, J5 Eco Soc's support the multimaster i2c ? We had ported 4.4 kernel on A core.

over 4 years ago

0 Chong Yu over 4 years ago

TI__Intellectual 1435 points

Mark

+1 Stanley Liu over 4 years ago in reply to Chong Yu

TI__Guru 50045 points

Hi,

Our SDK doesn't have support for multi-master.

Regards,
Stanley

0 Josmon Paul over 4 years ago in reply to Stanley Liu

Prodigy 20 points

Thanks for the feedback. . I had a look into the controller code of I2C and i can see that arbitration scenarios are handled in the code and is matching with the TRM.

Another option for us incase if arbitration support is not there is to control this scenario from the application . For eg: we will internally have a handshake between A core and M core application and will make sure both will not communicate to the I2c peripheral at the same time. Will that option workout here ?

0 Stanley Liu over 4 years ago in reply to Josmon Paul

TI__Guru 50045 points

Yes. You can use sync mechanism to allow 2 cores to share the same peripheral, i.e. I2C.

Regards,
Stanley

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multi master support for i2c on J5-Eco, J6