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Original question:

AM3352: VDDS power sequence with TPS65217C

AM3352: TPS65217C default power up sequence doesn't meet AM335x datasheet

Tony Tang
Mastermind 29152 points
Part Number: AM3352
Other Parts Discussed in Thread: TPS65217

I compared Powering the AM335x with the TPS65217x . (Rev. I) with AM335x datasheet power sequence, found LDO3(1.8V) and DCDC1(1.5V) sequence of TPS65217C doesn't meet AM335x requirement. which is right? Beaglebone Black follow document of powering the AM335x with the TPS65217x design.

  • 0
    TI__Expert 8275 points

    Hi Tony,

    I am working with TI experts and will follow up with you on this. Your observations appear valid to me at this time.

    Regards,

    Colin

  • 0
    TI__Expert 8275 points

    The issue is addressed in the PMIC app note, here.

    VDDS is ramped up before VDDS_DDR to avoid a problem with the sequencing. RTC-only cannot be supported with C and D versions as VDDS and VDDS_RTC are tied together to address the VDDS_DDR sequencing. 

    "TPS65217C is also targeted at the AM335x processor in the ZCZ package, but the DCDC1 output voltage is set to 1.5 V to supply DDR3 memory. This version does not support AM335x RTC-only operation."

  • 0 in reply to Colin Callaghan
    TI__Mastermind 29152 points

    Colin,

    I agree to connect 1.8V RTC and VDDS 1.8V together if doesn't use RTC only feature, my question is I did not find a power sequence figure in data sheet with  a 1.8V ramp up after VDDS_DDR(1.5V)

    From TPS65217C power sequence, the LDO3 1.8V ramp up after DCDC1 1.5V. And in datasheet, did not separate VDDS 1.8V and other 1.8V, but in the TPS65217 separate 1.8V to VDDS, RTC and VDDSHVx etc. VDDS and VDDS_RTC ramp up before VDDS_DDR, rest 1.8V ramp up after VDDDS_DDR. 

    Please point me which power supply sequencing figure in AM335x datasheet follow the TPS65217 PMIC app note. 

  • 0 in reply to Tony Tang
    TI__Expert 8275 points

    Tony,

    This workaround issue for this specific SoC+PMIC solution is not captured in the AM335 datasheet. The Power-Up Sequence for TPS65217C in Figure 6 and Table 6 of the App Note provides the timing diagram for the work around.

    Regards,

    Colin  

  • 0 in reply to Colin Callaghan
    TI__Mastermind 29152 points

    Colin,

    What is the workaround issue? 

    Do you mean AM335x power sequence can be 1.8V after VDDS_DDR?

  • 0 in reply to Tony Tang
    TI__Expert 8275 points

    Tony,

    The work around essentially is that VDDS and VDDS_RTC are tied together to address the VDDS_DDR sequencing issue.

    Regards,

    Colin

  • 0 in reply to Colin Callaghan
    TI__Mastermind 29152 points

    Colin,

    if customer doesn't push anymore, I won't ask more, but customer insist on asking the power sequence violation.

    I am not asking the VDDS_RTC, I am asking in the user guide there is a 1.8V rail(LDO3) ramp up after VDDS_DDR (DCDC1). I did not find such a power sequence in AM335x datasheet. Please just comments on this point. 

  • 0 in reply to Tony Tang
    TI__Mastermind 22421 points

    Hi Tony,

    I'm an Apps engineer supporting the TPS65217C PMIC. Having the 1.8V rail (LDO3) ramping up after VDDS_DDR (DCDC1) or vice versa doesn't violate the AM335x spec. They just both need to be high before the 3.3V rail starts ramping up. We generally avoid ramping up two rails at the same time for in-rush reduction and that's why you don't see them ramping up together in the TPS65217 documentation.

    Thanks,

    Brenda

  • 0 in reply to Brenda Diaz
    TI__Mastermind 29152 points

    Cruz,

    Thanks for clear and straight reply.

    Brenda Diaz said:
    Having the 1.8V rail (LDO3) ramping up after VDDS_DDR (DCDC1) or vice versa doesn't violate the AM335x spec. They just both need to be high before the 3.3V rail starts ramping up.

    But I did not find such description or figure in AM335x datasheet. maybe it is in some corner comments. would somebody point it to us. 

  • 0 in reply to Tony Tang
    TI__Mastermind 22421 points

    Hi Tony,

    The response to this latest question was provided by email. The processor sequence does not have a requirement for timing for 1.8V supplies vs. VDDS_DDR, they are in the same time slot and either can be powered up first/second.  

    Thanks,

    Brenda