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Original question:

66AK2G12: PCIe cable

66AK2G12: Modifying the PCIe cable

O.H
Mastermind 7200 points

Part Number: 66AK2G12

Hi experts,

Currently, a customer is trying to connect two K2G evaluation boards via PCIe.

Q1:According to the following thread, it says "No cable modification is required when using PE-FLEX1-G2-MMCX-12-TI1", is this correct?
https://e2e.ti.com/support/processors-group/processors/f/processors-forum/965755/66ak2g12-pcie-cable/3569010#3569010

According to the following document, if we want to connect two K2Gs via PCIe, we need to modify the cable, but I can't confirm this because the link is broken due to Wiki information.
https://software-dl.ti.com/processor-sdk-rtos/esd/docs/latest/rtos/index_device_drv.html#id14

Q2:If this cable needs to be modified, could you please share the information on the wiki?

Q3:How can I purchase PE-FLEX1-G2-MMCX-12-TI1, can I get it by contacting Adex Electronics directly?
http://www.adexelec.com/pe-flex1-4-8-16

If it is not available for purchase, it would be helpful to know if there is an alternative cable.

Best regards,
O.H

  • 0
    Mastermind 7200 points

    Hello,

    I'm sorry to rush you. What is the situation?

    The customer needs answers, so it would be helpful if you could share your progress with us.

    Best regards,
    O.H

  • 0 in reply to O.H
    TI__Mastermind 30986 points

    I'm sorry for the delay, I have asked for additional help on this. Thank you.

  • 0
    TI__Mastermind 27890 points

    Hello,

    A1: The answer is: "It depends". The modification is to ensure that both ends of the link are not providing the PCIe REF_CLK (bus clock contention). The cable (or the EP itself) should be modified to allow only the RC to supply the bus clock.

    A2: See above. Ensure that only the RC is sourcing the bus clock via the cable. The EP should sink the bus clock provided by the RC.

    A3: Yes, you would need to contact ADEX directly. I am not aware of another source for this cable.

  • 0 in reply to -DK-
    Mastermind 7200 points

    Hello DK,

    Thank you for your answer.

    -DK- said:

    A1: The answer is: "It depends". The modification is to ensure that both ends of the link are not providing the PCIe REF_CLK (bus clock contention). The cable (or the EP itself) should be modified to allow only the RC to supply the bus clock.

    A2: See above. Ensure that only the RC is sourcing the bus clock via the cable. The EP should sink the bus clock provided by the RC.

    I understood that we need to make sure that only the RC is supplying REF_CLK to the cable (i.e. the EP's REF_CLK is disconnected from the cable).

    We understood that we can also purchase and modify "PCIE-036-0200-EC-EM-85" as a means to obtain a cable with the above structure. We will check with AdexElectronics first.

    Best regards,
    O.H