Other Parts Discussed in Thread: AM1808, TPS65070
Hi,
Sorry for creating as new post but I have not received any support for the last few days, neither is an intimation of how much time It would take. The original post is here
http://e2e.ti.com/support/dsp/omap_applications_processors/f/42/p/100536/354959.aspx#354959
I have a custom board designed with TPS65070 and AM1808 and the design is the same as (after jury-rigging ) the AM1808 EVM kit ,except that the crystal is not connected to the OSCVSS but to the DGND.(but this is same as in and some how works in the EVAL kit, although it is against design guidelines)
I am doing a POR as well as a Warm Reset. I receive the RESETOUT from the AM1808 but the core of the chip doesnt come out of the reset.
- I have checked the power planes and the clock input and they are stable before I de-assert RESET.
- I don't recieve any signal on the UART interface (In the uart boot mode).
- When I try the same reset using a non-debounced signal I saomehow get a reset. I have noticed that in a non-debounced way there a lot of back to back resets given.Is this an issue with the core of the AM1808 not coming out of the reset cleanly??
- If so how is it possible that the uncontrolled (numerous consecutive RESETs) do the job??
I am kind of struck
