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[Omap3530] Chipselect problem on SPI3

David Bozec
Intellectual 400 points
Other Parts Discussed in Thread: OMAP3530

Hi,

 

I encounter a problem with the "Chipselect" pins on SPI3 bus on OMAP3530.
When I use CS0, it works perfectly, but when I try to use CS1, the corresponding pin is always on low level (chipselect activated).

I configured both CS0 and CS1 pins with same options, as following on uboot :

evm.h
    MUX_VAL(CP(ETK_D0_ES2 ),    (IEN  | PTD | DIS | M1)) /*SPI3_MOSI*/\
    MUX_VAL(CP(ETK_D1_ES2 ),    (IEN  | PTU | EN  | M1)) /*SPI3_MISO*/\
    MUX_VAL(CP(ETK_D2_ES2 ),    (IDIS | PTU | EN  | M1)) /*SPI3_CS0*/\
    MUX_VAL(CP(ETK_D3_ES2 ),    (IEN  | PTD | DIS | M1)) /*SPI3_CLK*/\
    MUX_VAL(CP(ETK_D7_ES2 ),    (IDIS | PTU | EN  | M1)) /*SPI3_CS1*/\



Since there is still a difference, I tried to configure in the kernel with the following lines :

board-omap3evm.c
static struct omap_board_mux board_mux[] __initdata = {
...
    OMAP3_MUX(ETK_D2, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP |OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_HIGH ),
    OMAP3_MUX(ETK_D7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP | OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_HIGH),
...



once again, CS0 works fine, but CS1 keeps low level at any time.

There is no MUX conflict with other pins, so I don't understand where is the mistake.

 

Thanks for your help,

Regards.

  • 0
    TI__Mastermind 28015 points

    Vostock

    I take it from your description that the CLK and SIMO/SOMI lines are all working ok.

    Could something be reconfigurint the CS1 line? Can you inspect the padconf register after you application is running to ensure that it is still correctly configured?

    Could there by a a short to 0v or something else driving the CS1 signal?

    When switching to channel 1, you are switching code to access the CH1 SPI registers rather CH0 registers?

      Paul M.

  • 0 in reply to PaulM
    Intellectual 400 points

    Hi Paul,

     

    That's right the CLK and SIMO/SOMI lines are all working ok.

    If something is reconfiguring the CS1 line, I can't find it. That was my first direction of search but I didn't found anything.

    I inspected padconf register and it is ok

    there is nothing shorting CS1 signal to 0V, I use the evm-board.

    Yes I change my code to access CH1 SPI registers.

     

    Regards.

     

  • 0 in reply to David Bozec
    Intellectual 400 points

    I forgot to note that I can't control the concerned PIN even in GPIO mode :(

  • 0 in reply to David Bozec
    TI__Mastermind 28015 points

    Vostock

    On the Mistral EVM the SPI3_CS1 (ETK_D7_ES2)  differs from the other spi signals in that it passes through a bus switch (U134) . If this switch is not enabled (default state) then the signal will not propagate to pin  B43 of the P18 expansion connector. U134 is enabled by driving EXP_nUSB2_EN low. 

    The pre-bus switch version of SPI3_CS1 (ETK_D7) signal is available on pin 16 of the ETM connector (P3) so you should be able to check for activity there first without modifying your code.

      Paul

  • 0 in reply to PaulM
    Intellectual 400 points

    You're right

    Here was my mistake.

    Thanks a lot.