AM5748: Connecting FPGA through PCIe to DSP

Part Number: AM5748

I’ve got question regarding connecting between A15 and DSP. We are trying to make proof of concept: connecting FPGA through PCIe to DSP.

As guy with Linux experience I have decided to first use A15 as a bridge. This bridge is just a simple PCIe driver which uses linux kernel API and after receiving some data it will be triggering DSP to handle received data. The same way it should work in opposite side: DSP->A15->PCIe->FPGA.

First question:
I do not know exactly how to make connection between DSP and A15. I thought about shared memory defined in DTS and propagated through resource table to DSP. In this case DSP will be triggered by simple IRQ on A15 side. What do you think about this idea? Is it good or not? We need quite low latency for transactions.
I’ve been working with J6+ and J6Eco SoCs and as far as I remember you are (Texas Instruments) providing VSDK but it has a very big latency. However do you have some similar framework but with better performance?

Second question:
How should we load DSP? I know that there is mechanism called as early-boot however until everything is not stabilized I am little afraid about this mechanism. Can we disable early-boot in uboot and dts then load dsp image via remoteproc mechanism?

Regards Bernd

over 4 years ago

0 Stanley Liu over 4 years ago

TI__Guru 50045 points

Hi,

Have you reviewed the IPC offered in SDK? You can find the documentation at the below link.

https://software-dl.ti.com/processor-sdk-linux/esd/docs/06_03_00_106/linux/Foundational_Components_IPC.html

Regards,
Stanley

0 jian35385 over 4 years ago in reply to Stanley Liu

TI__Mastermind 23125 points

On notes about low latency transfer between DSP<-> FPGA. :

>>This bridge is just a simple PCIe driver which uses linux kernel API and after receiving some data it will be triggering DSP to handle received data. The same way it should work in opposite side: DSP->A15->PCIe->FPGA.

You can let the Linux to enumerate PCIe then let DSP use the PCIe peripheral. Please see a similar description of this use case at:

https://e2e.ti.com/support/processors-group/processors/f/processors-forum/955011/am5726-share-pcie-gpmc-interface-between-arm-and-dsp-cores?tisearch=e2e-sitesearch&keymatch=dsp%25252520pcie#

Regards

Jian

0 BO over 4 years ago in reply to jian35385

TI__Genius 12760 points

Jian,

we’ve been trying yesterday to trigger interrupt on sitara board with connected PCIe FPGA. However we do not see anything.

I am not sure do we correct generates interrupt: FPGA configured as endpoint is sending data to Sitara board. But in /proc/interrupts I do not see any change. After modprobing our driver which assign to irq_no 172 (irq number generated by linux) we do not see any change too.
But we are able to write command register Sitara -> FPGA, read status register Sitara->FPGA->Sitara, read VID/DID and write/read data to/from specific BARs (0, 1 and shift those addresses).

Here are some logs:
Modprobing our driver:

cat /proc/interrupts/

Some additional info:
FPGA after sending to us memory write request caused: omap_l3_noc 44000000.ocp: L3 application error: target 5 mod:1 (unclearable)

Do you have any suggestions what can it be and how can we resolve it?

Regards, Bernd