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Not able to set TIM12RS in TGCR?

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Other Parts Discussed in Thread: OMAP-L138

I am trying to clear the TMR2->TGCR, TIM12RS bit by writing a 1 to that location. However, as I step through the code and watch the instruction execute, the TIM12RS bit does not get set. What can be holding TMR2 1:2 in reset?

I am using the Logic BSL code, which looks like this:

SETBIT(TMR2->TGCR, TIM12RS);

Any thoughts would be appreciated.

Thx,

MikeH

 

  •  

    Ok, problems persists. Here's more detail.

     

    I am initializing TIMR2 & TIMR3 as follows (per the modified Logic BSL):

    uint32_t USTIMER_init(void)

    {

    // configure timer 2 for free run.

    // 32-bit unchained mode, timer3:4 /16 prescaler.

     

    // enable muxed pins as gpio outputs and disable all related interrupts.

    // would need to also setup the pinmux register to select the gpio

    // function of these pins in order to use as gpio.

     

       TMR2->GPINT_GPEN = GPENO12 | GPENI12;

       TMR2->GPDATA_GPDIR = GPDIRO12 | GPDIRI12;

     

       // stop and reset timer.

       TMR2->TGCR = 0x00000000;

       TMR2->TCR = 0x00000000;

     

       // disable interrupts and set emulation to free run.

    //   TMR2->INTCTLSTAT = 0;

       TMR2->INTCTLSTAT = 1; //enable prdinten12 compare interrupt for my timer

       SETBIT(TMR2->EMUMGT, SOFT | FREE);

     

       // config timer2 in 32-bit unchained mode.

       // remove timer2 - 3:4 from reset.

       SETBIT(TMR2->TGCR, PRESCALER(TIMER23_DIV - 1) | TIMMODE_32BIT_UNCHAINED | TIM34RS );

     

       // init timer2 - 1:2 period....use full range of counter.

       TMR2->TIM34 = 0x00000000;

       TMR2->PRD34 = 0xFFFFFFFF;

     

       // start timer2 - 3:4.

       SETBIT(TMR2->TCR, ENAMODE34_CONT);

       SETBIT(TMR2->TCR, ENAMODE12_ONETIME);   

     

       // configure timer 3 for start/stop.

    // 32-bit unchained mode, timer3:4 /12 prescaler.

     

    // enable muxed pins as gpio outputs and disable all related interrupts.

    // would need to also setup the pinmux register to select the gpio

    // function of these pins in order to use as gpio.

       TMR3->GPINT_GPEN = GPENO12 | GPENI12;

       TMR3->GPDATA_GPDIR = GPDIRO12 | GPDIRI12;

     

       // stop and reset timer.

       TMR3->TGCR = 0x00000000;

       TMR3->TCR = 0x00000000;

     

       // disable interrupts and set emulation to free run.

       TMR3->INTCTLSTAT = 0;

       SETBIT(TMR3->EMUMGT, SOFT | FREE);

       // config timer3 in 32-bit unchained mode.

     

       SETBIT(TMR3->TGCR, PRESCALER(TIMER23_DIV - 1) | TIMMODE_32BIT_UNCHAINED);

       // init timer3 - 3:4 period....0 until someone calls delay().

       TMR3->TIM34 = 0x00000000;

       TMR3->PRD34 = 0x00000000;   

     

       return (ERR_NO_ERROR);

    }

     

    I am then trying to use TIMR2 as a one-shot timer that invokes HWI6 when it reaches it period count. Here are my functions.

     

    void MyTIMER_reset(void)

    {

       CLRBIT(TMR2->TGCR, TIM12RS);

       TMR2->TIM12 = 0x00000000;

    }

     

    void MyTIMER_set(uint32_t in_time)

    {

       TMR2->PRD12 = TICKS23_PER_US * in_time;

    }

     

    void MyTIMER_start()

    {

    SETBIT(TMR2->TCR, ENAMODE12_ONETIME);

    SETBIT(TMR2->TGCR, TIM12RS);

    }

     

    However, when I call MyTIMER_start() and step through the code, the TIM12RS bit does not get set (to enable the timer). What could keep TIMR2 from allowing the reset bit to be set? As you can see, I have enabled the TIMR2 for ONE TIME operation....??

    Guidance appreciated.

    Thx,

    MikeH

     

     

  • Ok. Progress. 

    I discovered that enabling the GPIO pins prevents the TIMR2 from operating. So I disabled the GPIO pins and can now disable the TIMR2->TCGR reset. HOWEVER, the timer will not run. I assume the timer should begin counting as soon as I clear the RESET?

    Suggestions appreciated.....

    Thx,

    MIkeH

     

  • Hmmmm.... This appears to be the wrong forum for my questions. Could someone move this post over to the OMAP-L138 forum?

    Thx,

    MikeH