When SPI Port of AM3352 is used as SLAVE, the clk width is limited (min_a：0.5P-3.12, max_a:0.5P+3.12) --- SPRS717L table 7-84
Is it require the clk width of MASTER is in the range of （min_a，max_a）as above?
what will occur if the CLK width of MASTER is larger than max_a?
