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OMAP L138 UPP Transfer Protocol

Jeffrey McCasland
Prodigy 140 points

Are there any specific requirements related to the time between two sequential UPP receive transactions?  i.e. how much delay is needed between UPP_CHX_Enable LO to UPP_CHx_Enable HI?  On my board with a theroetical transfer rate of 50MBytes/sec, I am able to achieve 29MBytes/sec transfer rate by adding delays between UPP cycles.  I can send a single burst of an 8k byte packet at 50MBytes per second with no problems.  However, when I send multiple 8k packets with a single upp clock cycle between the UPP transactions, my system hangs.  I am attempting to transfer a 1MByte block of data, 128 @ 8192 bytes at the full 50MByte data rate (upp_cha_clk = 12.5 MH/z, ddr mode).  Any clues?

 

Thanks,

 

Jeffrey McCasland

  • 0
    TI__Expert 8890 points

    Jeffrey,

    It should be valid to drive ENABLE low for one uPP clock cycle, then bring it high again.  Let me make sure I understand your transfer parameters correctly.  Please correct me if any of this is wrong:

    • uPP operating in receive mode
    • Single DMA transfer (128 lines, 8192 bytes each)
    • Transmitter is forcing a small delay between lines by driving ENABLE low

    If the above is correct, there is no reason why this should not work.  How much longer is the delay that allows your system to work properly?  Also, is it possible for you to try the entire transfer with no delay between data lines?