VIM

Hello,

The Cortex-R5 CPU has an integrated VIC port which by design is meant to speed up interrupt handling.  Its baseline feature however has some limitations in that it only defines 32 sources and is single core centric. To address VIC limitations TI has added the VIM. The VIM provides an interrupt processing system which allows for up to 1024 sources, and handles lock-step and safety requirements, and at the same time leverages the VICs interrupt acceleration features.   The VIM breaks up the 1024 interrupts as groups of 32.  The VIM processes all the interrupts with a similar goal as the VIC does for 32 but for 1024.  When it locates the highest priority active interrupt it will present the vector to the vectored interface and the flow will then progress logically much like you might understand happens for a simple VIC case.

The TDA4 TRM describes the VIM interface at 6.3.3.6 R5FSS Vectored Interrupt Manager (VIM).   TI's SDK provides reference implementation for VIM against TI's SYS/BIOS RTOS and for FreeRTOS.   The best way to understand the use model is to read the TRM chapter and then utilize interrupt APIs provided in the SDK.  Any concepts you understand from the VIC and its processing should help in digesting this.

Regards,

Richard W.