TDA4VM: How to configure a mdio phy address is clause 45(c45) access ?

Hi Gibbs,

Yes you need to configure the PHY for C45 access. You will have to check with the PHY manufacturer for that.

Regards

Vineet

Hi, Vineet 

Thanks you reply.

Follow your comment

>> Yes you need to configure the PHY for C45 access. 

My question is " How to configure tda4 mdio for C45 access?

Any sample code?

I just use this function in enetphy.c , but it return Mdio_readRegC45: PHY 3 is not configured for C45 access

Hi Gibbs,

If you see the code for EnetPhy_readC45Reg() it first reads the PHY and checks if the Clause 45 support is enabled. If it's not enabled then it returns the error you mentioned.

c45EnMask = CSL_MDIO_getClause45EnableMask(mdioRegs);

So, first you need to enable it in the PHY by talking to the manufacturer (Marvell), they will probably ask you to enable it by writing to some vendor specific register using MDIO. See enet/tools/debug_gels/cpsw_phyaccess_raw.c on how to do it.

We do not have any example for enabling C45 support in PHY because we do not have a TI PHY on the EVM which has C45 support.

If you have enabled it already and you still do not see this value being set then let us know.

Regards

Vineet

Hi, Vineet

I check to our vendor,  C45 is default working for Marvel 88Q2220.

You do not need extra setting for this phy chip.

so I try to check "c45EnMask" flag, it return 0.

check steps as below:

1. mdio.c, function "Mdio_open"

#if ENET_CFG_IS_ON(MDIO_CLAUSE45)
            if (ENET_FEAT_IS_EN(hMod->features, MDIO_FEATURE_CLAUSE45))
            {
                ENETTRACE_INFO("[mdio.c] Mdio_open() ENET_CFG_IS_ON MDIO_CLAUSE45 ON\n");
                CSL_MDIO_setClause45EnableMask(mdioRegs, mdioCfg->c45EnMask);
            }
#endif

2. mdio.c, function "Mdio_readRegC45()"

static int32_t Mdio_readRegC45(CSL_mdioHandle mdioRegs,
                               uint32_t userCh,
                               uint32_t mmd,
                               uint8_t phyAddr,
                               uint16_t reg,
                               uint16_t *val)
{
    bool isComplete;
    uint32_t c45EnMask;
    int32_t status;   

    c45EnMask = CSL_MDIO_getClause45EnableMask(mdioRegs);
    ENETTRACE_INFO("[mdio.c] Mdio_readRegC45()-> c45EnMask = 0x%x\n", c45EnMask);

    if (ENET_IS_BIT_SET(c45EnMask, phyAddr))
    {
        ENETTRACE_INFO("[mdio.c] Mdio_readRegC45()-> c45EnMask bit set\n");

        /* Wait for any ongoing transaction to complete */
        do
        {
            isComplete = CSL_MDIO_isPhyRegAccessComplete(mdioRegs, userCh);
        }
        while (isComplete == FALSE);

        /* Initiate register read */
        status = CSL_MDIO_phyInitiateRegReadC45(mdioRegs, userCh, phyAddr, mmd, reg);
        ENETTRACE_ERR_IF(status != CSL_PASS,
                         "failed to initiate PHY %u C45 MMD %u register %u read: %d\n",
                         phyAddr, mmd, reg, status);

        /* Wait for register read transaction to complete */
        if (status == CSL_PASS)
        {
            do
            {
                isComplete = CSL_MDIO_isPhyRegAccessComplete(mdioRegs, userCh);
            }
            while (isComplete == FALSE);
        }

        /* Get the value read from PHY register once transaction is complete */
        if (status == CSL_PASS)
        {
            status = CSL_MDIO_phyGetRegReadVal(mdioRegs, userCh, val);
            ENETTRACE_ERR_IF(status == CSL_ETIMEOUT,
                             "C45 register read %u was not acknowledged by PHY %u: %d\n",
                             reg, phyAddr, status);
            ENETTRACE_ERR_IF(status == CSL_EFAIL,
                             "failed to read PHY %u C45 MMD %u register %u: %d\n",
                             phyAddr, mmd, reg, status);
        }
    }
    else
    {
        ENETTRACE_INFO("[mdio.c] Mdio_readRegC45()-> c45EnMask bit not set\n");
        ENETTRACE_ERR("PHY %u is not configured for C45 access\n", phyAddr);
        status = ENET_EPERM;
    }

    return status;
}

c45EnMask always return 0

Gibbs

Hi Gibbs,

Sorry for the delay.

I need to check internally and get back to you why the register read is not working. Please give me 2 weeks time.

Regards

Vineet

Vineet,

Got it 

Many Thanks

Gibbs

Hi Gibbs,

Is this issue still open at your end ? One thing to check would be if this is a generic MDIO issue with Marvel 88Q2220 or something C45 specific ?

Few things to check would be

1. Is the PHY initialized and working correctly ? Are you able to send and receive packets ?

2. Can you check by enabling Clause 22 support in this PHY and then querying the PHY registers ? to rule out C45 specific issue ?

Regards

Vineet

Hi, Roy :

1. We very sure 88Q2220 works well on our board, because Marvel FAE help us do some HW re-work, and use some mdio 

diagnosis tools to check it. you can check with Rio, he knows how to do this test.

2. PHY can not initialized because of mdio communication problems, even we use C22/C45 protocol for 88Q2220

Hi Gibbs,

In that case, are you able to read basic registers like status and control regs from 88Q2220  ? What values do you read ? I am not blaming the other PHY, just want to differentiate between basic MDIO and C45 specific issues.

Regards

Vineet

Hi, Vineet :

>> In that case, are you able to read basic registers like status and control regs from 88Q2220 

we just read basic register 0x02/0x03 for device id reading

Marvel  diagnosis tools can use c22/c45 protocol reading

phy2
vendor id
P2R14=0x002b	
device id
P2R14=0x0b20	
 
 
phy4
vendor id
P4R14=0x002b	
device id
P4R14=0x0b20