HPI strange behaviour (or is it?)

Graeme,

Graeme Parker said:

I have HPIA set to 0x00808000 (internal memory)

This local memory address is only available to a DSP core to access its own local memory. Each core accesses its own memory using this address, so it is not a visible address for any other bus master. You must use the Global Address to access any of the DSP cores' internal L1/L2 memory with the HPI.

Graeme Parker said:

Using the FPGA I can access the HPIC register (set to 0)

I am surprised that HPIC.HRDY bit 3 is not 1. Are all of the other bits supposed to be 0?

Graeme Parker said:

I have targeted external DDR2 at 0xE0000000 with the same result.

This means there is something other than the Global address problem going on. The increment-by-1 is also a bad indication, as you know. The fact that you can write and read any value seems to indicate good hardware connections. Can you try using the Dual-HPIA mode and write a value to HPIAR then a different value to HPIAW? Then read back HPIAR and then HPIAW and see how they behave. This is to make sure "bus history" is not masking a problem.

This is all I can think of to look at right now. Check and double-check the hardware signals to make sure they match the behavior shown in the User's Guide.

Regards,
RandyP

Thanks for the ideas.

According to the 6472 datasheet, software handshaking using the HRDY bit is not supported. I took this to mean that the HRDY bit value is either not readable (returns 0) or not a reliable internal ready indication. From the CPU side, HRDY always reads as '0'.

I thought about if it could be a bus history issue, but because Code Composer Studio reported the same values in the HPI registers as my FPGA was writing, I assumed this was all ok. Anyway, I enabled the dual HPIA mode and can write and read both HPIAR and HPIAW. So I'm sure it's not bus history now.

Yeah, it's weird! I have looked many times at the HPI signals and they always look spot-on! For the HPIA to count by just 1 after each HPID write, there must be something particularly strange going on. I wonder if one of your chip design experts would have an idea how this could happen.

I've noticed that the HPIRST bit reads as a '1' if the boot mode is set to MAC or I2C. Is this deliberate or an indication that we have another problem :(

Graeme,

Have you tried accessing the Global addresses like 0x10200000 and 0x10800000 through the HPI port? There could be other issues with DDR2, so I am curious whether correcting the 0x00800000 local address would affect your results.

Your point about boot modes made me ask whether you are using the C6472 in HPI boot mode or just trying to use it after booting some other way.

It would be a good test to put the C6472 into HPI boot mode and then to do some writes and reads from the host, leaving the C6472 in the boot mode. In HPI boot mode, the Boot ROM will make sure everything is set correctly to allow accesses. Like above, try accessing 0x10200000 and 0x10800000, especially since DDR2 would not be initialized, yet.

Regards,
RandyP

Hi

Yes, I've tried those global addresses. Using Code Composer Studio (CCS) I can see tha tthe HPIAW and HPIAR registers contain the correct values. But still, when I write to the HPID (with auto-increment), the address registers count by 1 and the memory contents do not change.

The C6472 is in HPI mode.

Thanks for your suggestions,

Graeme.

Hi,

two other things to check:

1. make sure you refresh your memory view window in CCS

2. In you memory view please also look at the cache check boxes and try to uncheck L1D.

Kind regards,

one and zero

Thanks. When I have some spare time (I'm concentrating on booting using good old I2C now) I'll have a look at the L1D cache check boxes.

However, I can perform host accesses when CCS is not running (after a CPU power cycle), and I can read the HPIAW and HPIAR registers which still show that they increment by 1. This must surely be the strangest behaviour.

I have now checked everything that has been mentioned and am not making any progress. From my host, I can read and write to the HPIA registers, but it still remains that when the host writes a word, then the HPIA register increments by 1 and the data does not get written to any targetted memory.

There must be an explanation for why the increment is only 1 (and not 4 as expected). Does any TI guru want to investigate what could cause this? Thanks.

Graeme,

Please confirm that you have set the boot mode to HPI boot. This will ensure that any settings are valid for the HPI port.

Please try reads and writes to the Global internal addresses of L2 or SL2 and use the non-incrementing address mode where HCNTL[1:0]=11b. Reading and writing need to work, regardless of the mis-incrementing.

In CCS, initialize and clear all memory. Run a test on your host to write unique values throughout the 32-bit addressable memory space. Then look through CCS to see if anything was written anywhere. Repeat the other way around by using CCS to write unique values in all valid memory locations then use the HPI to read everything looking for anything that is non-zero.

Check again your board connections and look at them on a scope or logic analyzer.

Are you using 32-bit mode or 16-bit mode for the HPI interface?

Can you confirm all the control bits in HPIC work as expected? Set/clear HINT from CCS, set/clear DSPINT from HPI and see the result in CCS, etc.

There will be a solution, but finding it is proving to be difficult.

Regards,
RandyP

Boot mode is set to 0001 (HPI).

I've tried accessing address 0x10800000, and although I can write and read the HPIA register, writing/reading from L2 (using non-incrementing HPID) always returns 0.

I'll skip your suggestion about writing values throughout all memory spaces for the moment.

I can see the signals using Xilinx's ChipScope utility as they are generated by an FPGA. I know this doesn't mean that they are actually connected to the DSP, but as I can reliably read/write HPIA I'm sure that the connections are good.

Ah, 32-bit HPI mode. How do I enable that on the C6472? It's only got a 16-bit bus.

HPIC seems ok. I've just set the HINT via the CPU and verified that the host can clear this by writing this bit as '1'.

Thanks for your continued support.

Well, as nobody seems to know the solution to this I'll post what I've just discovered in the last 5 minutes.

Remember that I said that for every HPI write I performed the HPIA register would increment by 1, and we all agreed that this was wrong and should inc by 4? That was a massive clue! The value you have to write to the HPIA register in the C6472 is the address / 4. So to access DDR at address 0xE0000000 you set HPIA to 0x38000000.

Did anyone at TI know that?!

Don't worry, it's only 6 weeks wasted time.