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AM6442: [AM64x Family] About access frequency to QSPI Memory

Tsuka-shi
Prodigy 130 points
Part Number: AM6442

I plan to connect to QSPI Memory using the Octal Serial Peripheral Interface (OSPI).
The QSPI Memory supports operation at 108MHz.
In Chapter 12.3.2.4.2.1 of TRM, it is described that an external loopback is required to operate higher than 50MHz.
On the other hand, in Table 12-1726 of TRM, it is described DQS is "not use" in Quad Read / Write.
Is it impossible to operate at 50MHz or higher with Quad Read / Write?

  • 0
    TI__Guru 63125 points

    You need to implement the External Board Loopback connection topology described in the OSPI and QSPI Board Design and Layout Guidelines section of the AM64x Datasheet.

    Please read this section of the datasheet and let me know if you have any further questions.

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 130 points

    I have read "9.3.2 OSPI and QSPI Board Design and Layout Guidelines" in Datasheet many times.
    The chapter does not provide the answer to my question.
    Please tell me specifically where it is listed.
    Or please answer.

    "Is it impossible to operate at 50MHz or higher with Quad Read / Write?"

  • 0 in reply to Tsuka-shi
    TI__Guru 63125 points

    The External Board Loopback connection topology described in the OSPI and QSPI Board Design and Layout Guidelines section of the AM64x Datasheet is not using DQS from a QSPI or OSPI device. This topology is basically inserting a PCB delay into the receive data capture clock path that is equal to the PCB delay of the AM64x clock going to the QSPI device plus the PCB delay of QSPI data returning to AM64x.

    This is done by sending one clock from the AM64x device directly to the QSPI device, while also sending an equivalent clock out of another AM64x pin through a PCB delay that loops back to the AM64x DQS pin. In this mode of operation, the AM64x DQS pin is not being used as a data strobe input. The AM64x DQS input is being used as a delayed receive clock. This is the external loopback topology that is expected when operating QSPI or OSPI devices over 50 MHz when they do not provide a data strobe output.

    You need to perform a timing analysis of the OSPI peripheral using timing parameters from the AM64x datasheet and your QSPI device datasheet, along with respective PCB delays to determine the maximum operating frequency supported by this combination of devices.  

    Regards,
    Paul

  • 0 in reply to peaves
    Prodigy 130 points

    Thanks for your reply.
    In TRM Rev.B Table 12-3231, DQS is described as "Not used" when set as 6pin SPI Quad Read Write.
    Is this a mistake and does it mean that DQS can be used as a "loopback clock input"?

  • +1 in reply to Tsuka-shi
    TI__Guru 63125 points

    After further review of the TRM, I determined Table 12-3231 in revision B of the TRM describes module pins, not device pins. Module pins are internal ports of the OSPI module. As mentioned in previous reply, QSPI devices do not have a DQS output. To achieve adequate timing margin for faster data transfer with QSPI, we use an external PCB delayed loopback clock which is input to the device DQS pin. However, this delayed clock is not connected to the module DQS pin. That is why the table says DQS is not used for QSPI. 

    The DQS row of Table 12-3231 has a note attached that describes how a looped back clock is used. Therefore, the TRM already addresses your question.

    You can see the looped back clock path from the DQS device pin in the OSPI Overview Figure 12-1508.

    Regards,
    Paul