McASP Loopback mode - receive signals

No the loopback occurs internal to the chip so you won't see the values also reflected on the AHCLKR/ACLKR pins. Section 2.4.8 of the McASP guide has more information on that.

If any values are marked as "Reserved" in the datasheet or user guide, they should be programmed with the value shown in "Value" if there is uncertainty, which is usually 0.

Jeff

Ok, thanks for the reply.

If I have the McASP in loopback mode, will the data be transmitted out if the transmit portion is setup properly, but not the receive?  Another way of asking is: does it require that the data be received properly, in order for the transmitter to work ... or can TX data just be blasted out regardless.  If the latter, I can focus on just getting the transmission part working first.

Robert

The loopback mode just acts as an internal loop from the TX to the RX pins. You will still have to take care of setting up the McASP receive buffer and handling the data, just as if there were an external loop on your board.

If you have a scope, you can still see all of the TX data on the pins, so you can debug that way to make sure you actually have data streaming out.

Jeff

Ok, thanks.  If data will stream out TX, regardless whether it's being read by anything (which I think you just confirmed it will), I'll just focus on that initially.

Right now, I have all the TX signals - AHCLKX, ACLKX and AFSX, but nothing out the actual AXR13 data line for the number 13 serializer being used, even though my program continually tries to feed XBUF13 (if XDATA is YES).

DLBCTL = 0x00000007 ( DLBEN, XMTEVEN, XMTCLK ).  

Solution to getting the TX data streaming was to also set the associated pinmux to AXR13:

CSL_FINST( sys0Regs->PINMUX1, SYSCFG_PINMUX1_PINMUX1_11_8, AXR0_13 );

But if I stop the emulator, after generating all the expected McASP TX signals ... in order to be successful again (get all McASP signals generated properly), I need to "Terminate All" in CCSV4, and re-connect, re-load and run again.

Is there a way to reset the McASP module short of this, programatically?  I tried to set the McASP module to disable during program startup, via the PSC, before enabling it, but that didn't seem to resolve it.

Robert

Robert,

Robert said:

But if I stop the emulator, after generating all the expected McASP TX signals ... in order to be successful again (get all McASP signals generated properly), I need to "Terminate All" in CCSV4, and re-connect, re-load and run again.

This behavior is expected as per the Operation Section of the McASP User's Guide. Refer to the initialization section, specifically step 8.

I would recommend reading through the user guide in detail as it will contains the information to most of the issues you have run into with your project.

Robert said:

Is there a way to reset the McASP module short of this, programatically?  I tried to set the McASP module to disable during program startup, via the PSC, before enabling it, but that didn't seem to resolve it.

 Yo don't necessarily have to terminate your emulation session with the device, you can simply halt the program execution, then reset the system, then reset the PC of the CPU. This will put to the device into a soft- POR reset state.

Drew Abuan said:

Robert,

This behavior is expected as per the Operation Section of the McASP User's Guide. Refer to the initialization section, specifically step 8.

I would recommend reading through the user guide in detail as it will contains the information to most of the issues you have run into with your project.

I have read the manual in detail, but there’s a lot of details, aren’t there?  Eventually I would likely find a solution to whatever question is asked here after reading enough, and trying enough things.  And I try to do due dilligence.  But it’s a complicated part ... more so than any of the many TI DSP’s I’ve used before, so the (patient) assistance here is appreciated.  And isn’t that what these forumns are for ... helping improve TI customer productivity, via application engineer insight.  I’d guess that anything learned here would likely be of use to any future engineers trying solve a similar problem, while navigating through a stifling amount of detail associated with this part, to find an answer possibly hidden amongst realms of other details in the manuals.  And in that respect, I always try to relay anything associated with the inquiries here, via a straightforward followup to thread when possible, for future benefit of others.

I was not stating my experience for confirmation, which is described in detail in the manual, but to suggest it’s impact on productivity, and ask for a possibly easier way to get the McASP in a clean state, short of taking everything down and back up.  Which you’ve suggested below, I hope.  Please see the follow inquiry to it.

Drew Abuan said:

 Yo don't necessarily have to terminate your emulation session with the device, you can simply halt the program execution, then reset the system, then reset the PC of the CPU. This will put to the device into a soft- POR reset state.

 

What do you mean by reset the PC?  I interpret that as setting the PC in the Core Registers window.  But that fails, after performing the System Reset, with a pop-up implying because the “target is being held in reset”.

Are you connecting to and running code on the ARM or DSP? If you are using the DSP, it is initially asleep after a system reset.

Try changing your boot mode pins on the EVM to Emulation Debug, which should automatically wake up the DSP after reset.

I'm connecting to and running code on the DSP.  I changed the EVM to Emulation Debug, but now end up in the weeds (NOP's) after 1) performing a System Reset and then 2) setting the PC back to the start of main() and running.  I can reset the PC back to main() and run after performing a CPU Reset, but that doesn't reset the McASP signals.

Thanks,

Robert

P.S.  Per the Logic L138 documenation, Emulation Debug was set by changing pins 5 and 8 of S7 to ON ( BOOT[1] and BOOT[4] ) .

Does your code have any sections in DDR2? If so a system reset will clear all the configuration. The easiest way would be to reconnect to the target which will run the GEL on_connect fuctions which you may be relying on. Otherwise you can manually run the GEL functions to set up the PLLs and DDR.

Jeff

Robert said:

What do you mean by reset the PC?  I interpret that as setting the PC in the Core Registers window.  But that fails, after performing the System Reset, with a pop-up implying because the “target is being held in reset”.

I guess that was a little too vague. When you reset the system via Emulator Session (make sure it's the system and not just the CPU), it will perform a soft Power On Reset (POR). This will force the PC to be returned to it's POR reset address. You'll need to 'restart' the program, which will initialize the CPU with the C environment, then halt the emulation logic at main(). This all can be done without having to terminate the debug session. Hope this clarifies things.

The 'System Reset'  will also reset the McASP state machines, logic back to it's original state along with a CPU POR.

jc said:

Does your code have any sections in DDR2? If so a system reset will clear all the configuration. The easiest way would be to reconnect to the target which will run the GEL on_connect fuctions which you may be relying on. Otherwise you can manually run the GEL functions to set up the PLLs and DDR.

Jeff

My code shouldn't be using any DDR2 sections.

Ok.  A console script I’ve come up with ends up re-loading the GEL file on connect, including running those PLL and DDR functions. 

Thanks,

Robert

Drew Abuan said:

The 'System Reset'  will also reset the McASP state machines, logic back to it's original state along with a CPU POR.

Per your followup, I tried these steps:

    1) get system up and running

    2) Halt

    3) Target->System Reset

    4) Target->Restart

But when stopping, it’s off in the weeds (NOPs), even though I had set a breakpoint at main().

I’ve put together a console script, though, that appears to take care of everything, including the McASP signals reset.  I can try any suggested changes to the process above, but otherwise am ok with the script approach, which is relatively quick and automated.

Thanks,

Robert

Here’s the script I’ve come up with that appears to reset everything (including McASP signals), and restart. 

In “Scripting Console”, type:

loadJSFile this_script_file.js

That will automatically call run().  Each next time, in the same console window, first type quit, followed by run.

---------------------------------------------------------------------------------------------------

importPackage( Packages.com.ti.debug.engine.scripting )

importPackage( Packages.com.ti.ccstudio.scripting.environment )

importPackage( Packages.java.lang )

run();

var script

function quit( val )

{

    debugSession.terminate();

    debugServer.stop();

}

function run()

{

    script = new Packages.com.ti.ccstudio.scripting.environment.ScriptingEnvironment.instance()

    script.setScriptTimeout( 9000 )

     print( "\nStart....\n" );

    debugServer = script.getServer( "DebugServer.1" )

    debugServer.setConfig( insert path to .ccxml file being used here );

    debugSession = debugServer.openSession( "Texas Instruments XDS100v1 USB Emulator_0/C674X_0" );

    try

    {

        print( "connect" );

        debugSession.target.connect();

    }

    catch (ex)

    {

        print( "\t- cannot connect\n" );

    }

    try

    {

        print( "reset" );

        debugSession.target.reset();

    }

    catch (ex)

    {

        print( "\t- cannot reset" );

    }

    try

    {

        print( "load" );

        debugSession.memory.loadProgram( insert path to .out file to load here );

    }

    catch (ex)

    {

        print( "\t- cannot load\n" );

    }

    try

    {

        print( "run" );

        debugSession.target.runAsynch();

    }

    catch (ex)

    {

        print( "\t- cannot run\n" );

    }

}

Hi Robert,

  Generally speaking, the above approach will work. Do you have a GEL file that does some additional configuration when it connects to the target? If so, the GEL file commands will not be re-executed with the above approach, and you will need to pull the setup into your program in order to make it successful.

Your script sounds like it works well - so you can stick with this approach if you are happy with it.

Drew,

There is a GEL file that does the configuration at each connect.

I'm still at a dead-end on getting the received data for the loopback.  I can't go to your example exactly, because that's not the solution I'm designing too (where the receive clock comes externally, etc).  But I did use that as a basis for what I'm trying to do.  Really, it's pretty simple ... the TX clocks are all driven from internally, ASYNC = 0, so the RX clocks should be the same as TX.  The TX side all looks fine .. clocks are at the rate I've specified, and I see the data out on AXR13.  But any reads that occur on the RX side are wrong ... either all 0xffffffff or 0xfffdffff.

I've included the register settings currently being used below.  They should be fairly evident, because of using the TI macros and defines for them.  Could you, or someone else, please review these settings, to see if there is anything obviously wrong about what I'm doing.  The targeted configuation is:

    loopback, even-ord

    AXR12 = RX

    AXR13 = TX

    AHCLKX = 24 Mhz

    ACLKX = 800 kHz

    AFSX = 12.5 kHz

I've listed the initialization first, then the start-up.

 Initialization

g_mcasp_regs->GBLCTL = 0;

// put the mcasp tx clocks in reset
//---------------------------------

CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XFRST, RESET );
CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XSMRST, RESET );
CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XSRCLR, CLEAR );
CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XHCLKRST, RESET );
CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XCLKRST, RESET );

// put the mcasp rx clocks in reset
//--------------------------------

CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RFRST, RESET );
CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RSMRST, RESET );
CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RSRCLR, CLEAR );
CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RHCLKRST, RESET );
CSL_FINST( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RCLKRST, RESET );

// disable fifo's
//---------------

CSL_FINST( g_afifo_regs->WFIFOCTL, AFIFO_WFIFOCTL_WENA, DISABLED );
CSL_FINST( g_afifo_regs->RFIFOCTL, AFIFO_RFIFOCTL_RENA, DISABLED );

// leave all receive regs unmasked
//---------------------------------

CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK31, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK30, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK29, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK28, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK27, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK26, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK25, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK24, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK23, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK22, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK21, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK20, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK19, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK18, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK16, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK15, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK14, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK13, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK12, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK11, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK10, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK9, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK8, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK7, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK6, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK5, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK4, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK3, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK2, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK1, NOMASK );
CSL_FINST( g_mcasp_regs->RMASK, MCASP_RMASK_RMASK0, NOMASK );

// receive bit
// - 32 bit, msb first, pad with 0, 32 bit, no rotation, periph port (for now)
//-----------------------------------------------------------------------------

CSL_FINST( g_mcasp_regs->RFMT, MCASP_RFMT_RDATDLY, 1BIT );
CSL_FINST( g_mcasp_regs->RFMT, MCASP_RFMT_RRVRS, LSBFIRST );
CSL_FINST( g_mcasp_regs->RFMT, MCASP_RFMT_RPAD, ZERO );
CSL_FINST( g_mcasp_regs->RFMT, MCASP_RFMT_RSSZ, 32BITS );
CSL_FINST( g_mcasp_regs->RFMT, MCASP_RFMT_RROT, NONE );
CSL_FINST( g_mcasp_regs->RFMT, MCASP_RFMT_RBUSEL, VBUS );

// receive frame sync
//-------------------

CSL_FINST( g_mcasp_regs->AFSRCTL, MCASP_AFSRCTL_RMOD, I2S );
CSL_FINST( g_mcasp_regs->AFSRCTL, MCASP_AFSRCTL_FRWID, WORD );
CSL_FINST( g_mcasp_regs->AFSRCTL, MCASP_AFSRCTL_FSRM, INTERNAL );
CSL_FINST( g_mcasp_regs->AFSRCTL, MCASP_AFSRCTL_FSRP, RISINGEDGE );

// receive bit clock
//------------------

CSL_FINST( g_mcasp_regs->ACLKRCTL, MCASP_ACLKRCTL_CLKRP, FALLINGEDGE );
CSL_FINST( g_mcasp_regs->ACLKRCTL, MCASP_ACLKRCTL_CLKRM, INTERNAL );
CSL_FINS( g_mcasp_regs->ACLKRCTL, MCASP_ACLKRCTL_CLKRDIV, MCASP_CLKDIV );

//
//-------------------------------------------------------------------------------

CSL_FINST( g_mcasp_regs->AHCLKRCTL, MCASP_AHCLKRCTL_HCLKRM, INTERNAL );
CSL_FINST( g_mcasp_regs->AHCLKRCTL, MCASP_AHCLKRCTL_HCLKRP, NOTINVERTED );
CSL_FINS( g_mcasp_regs->AHCLKRCTL, MCASP_AHCLKRCTL_HCLKRDIV, MCASP_HCLKDIV );

// receive tdm time slot - 0, 1 active
//------------------------------------

CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS31, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS30, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS29, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS28, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS27, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS26, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS25, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS24, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS23, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS22, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS21, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS20, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS19, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS18, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS17, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS16, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS15, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS14, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS13, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS12, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS11, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS10, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS9, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS8, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS7, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS6, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS5, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS4, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS3, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS2, INACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS1, ACTIVE );
CSL_FINST( g_mcasp_regs->RTDM, MCASP_RTDM_RTDMS0, ACTIVE );

// disable all rcv irqs
//---------------------

CSL_FINST( g_mcasp_regs->RINTCTL, MCASP_RINTCTL_RSTAFRM, DISABLE );
CSL_FINST( g_mcasp_regs->RINTCTL, MCASP_RINTCTL_RDATA, DISABLE );
CSL_FINST( g_mcasp_regs->RINTCTL, MCASP_RINTCTL_RLAST, DISABLE );
CSL_FINST( g_mcasp_regs->RINTCTL, MCASP_RINTCTL_RDMAERR, DISABLE );
CSL_FINST( g_mcasp_regs->RINTCTL, MCASP_RINTCTL_RCKFAIL, DISABLE );
CSL_FINST( g_mcasp_regs->RINTCTL, MCASP_RINTCTL_RSYNCERR, DISABLE );
CSL_FINST( g_mcasp_regs->RINTCTL, MCASP_RINTCTL_ROVRN, DISABLE );

//

CSL_FINST( g_mcasp_regs->RCLKCHK, MCASP_RCLKCHK_RPS, DIVBY4 );

CSL_FINS( g_mcasp_regs->RCLKCHK, MCASP_RCLKCHK_RMIN, 0x2F );
CSL_FINS( g_mcasp_regs->RCLKCHK, MCASP_RCLKCHK_RMAX, 0x35 );

// all tx unmasked
//----------------

CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK31, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK30, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK29, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK28, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK27, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK26, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK25, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK24, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK23, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK22, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK21, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK20, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK19, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK18, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK17, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK16, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK15, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK14, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK13, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK12, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK11, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK10, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK9, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK8, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK7, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK6, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK5, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK4, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK3, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK2, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK1, NOMASK );
CSL_FINST( g_mcasp_regs->XMASK, MCASP_XMASK_XMASK0, NOMASK );

CSL_FINST( g_mcasp_regs->XFMT, MCASP_XFMT_XDATDLY, 1BIT );
CSL_FINST( g_mcasp_regs->XFMT, MCASP_XFMT_XRVRS, LSBFIRST );
CSL_FINST( g_mcasp_regs->XFMT, MCASP_XFMT_XPAD, ZERO );
CSL_FINST( g_mcasp_regs->XFMT, MCASP_XFMT_XSSZ, 32BITS );
CSL_FINS( g_mcasp_regs->XFMT, MCASP_XFMT_XPBIT, 0 );
CSL_FINST( g_mcasp_regs->XFMT, MCASP_XFMT_XROT, NONE );
CSL_FINST( g_mcasp_regs->XFMT, MCASP_XFMT_XBUSEL, VBUS );

// tx frame sync control
//----------------------

CSL_FINST( g_mcasp_regs->AFSXCTL, MCASP_AFSXCTL_XMOD, I2S );
CSL_FINST( g_mcasp_regs->AFSXCTL, MCASP_AFSXCTL_FXWID, WORD );
CSL_FINST( g_mcasp_regs->AFSXCTL, MCASP_AFSXCTL_FSXM, INTERNAL );
CSL_FINST( g_mcasp_regs->AFSXCTL, MCASP_AFSXCTL_FSXP, RISINGEDGE );

// tx clock control
//------------------------------------------

CSL_FINST( g_mcasp_regs->ACLKXCTL, MCASP_ACLKXCTL_CLKXP, RISINGEDGE );
CSL_FINST( g_mcasp_regs->ACLKXCTL, MCASP_ACLKXCTL_ASYNC, SYNC );
CSL_FINST( g_mcasp_regs->ACLKXCTL, MCASP_ACLKXCTL_CLKXM, INTERNAL );
CSL_FINS( g_mcasp_regs->ACLKXCTL, MCASP_ACLKXCTL_CLKXDIV, MCASP_CLKDIV );

// transmit high frequency, ahclkx, generated internally from mcasp auxclk, which
// is sys clock = 24 Mhz
//-------------------------------------------------------------------------------

CSL_FINST( g_mcasp_regs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXM, INTERNAL );
CSL_FINST( g_mcasp_regs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXP, NOTINVERTED );
CSL_FINS( g_mcasp_regs->AHCLKXCTL, MCASP_AHCLKXCTL_HCLKXDIV, MCASP_HCLKDIV );

// tx tdm, 0 & 1 active for i2s
//-----------------------------

CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS31, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS30, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS29, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS28, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS27, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS26, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS25, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS24, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS23, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS22, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS21, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS20, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS19, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS18, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS17, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS16, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS15, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS14, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS13, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS12, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS11, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS10, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS9, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS8, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS7, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS6, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS5, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS4, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS3, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS2, INACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS1, ACTIVE );
CSL_FINST( g_mcasp_regs->XTDM, MCASP_XTDM_XTDMS0, ACTIVE );

// all tx irq disabled
//--------------------

CSL_FINST( g_mcasp_regs->XINTCTL, MCASP_XINTCTL_XSTAFRM, DISABLE );
CSL_FINST( g_mcasp_regs->XINTCTL, MCASP_XINTCTL_XDATA, DISABLE );
CSL_FINST( g_mcasp_regs->XINTCTL, MCASP_XINTCTL_XLAST, DISABLE );
CSL_FINST( g_mcasp_regs->XINTCTL, MCASP_XINTCTL_XDMAERR, DISABLE );
CSL_FINST( g_mcasp_regs->XINTCTL, MCASP_XINTCTL_XCKFAIL, DISABLE );
CSL_FINST( g_mcasp_regs->XINTCTL, MCASP_XINTCTL_XSYNCERR, DISABLE );
CSL_FINST( g_mcasp_regs->XINTCTL, MCASP_XINTCTL_XUNDRN, DISABLE );

// tx clock check control
//-----------------------
//
// mcasp clock = ( sysclk / 2 ) = ( 300 / 2 ) = 150 Mhz
//
// then xmax & xmin check will be made to use / 4 from
// that = 37.5 Mhz
//
// xmax = prescale by 4 = ( 150 / 4 ) = ( 37.5 Mhz )
//
// 32 / 24 Mhz = 1.333 us * 37.5 Mhz = 50
//
// so make 47 (0x2f) and 53 (0x35)
//
//----------------------------------------------------------------

CSL_FINST( g_mcasp_regs->XCLKCHK, MCASP_XCLKCHK_XPS, DIVBY4 );

CSL_FINS( g_mcasp_regs->XCLKCHK, MCASP_XCLKCHK_XMIN, 0x2F );
CSL_FINS( g_mcasp_regs->XCLKCHK, MCASP_XCLKCHK_XMAX, 0x35 );

// tx = serializer 11, rx = serializer 12
//---------------------------------------

CSL_FINST( g_mcasp_regs->SRCTL12, MCASP_SRCTL12_SRMOD, RCV );
CSL_FINST( g_mcasp_regs->SRCTL13, MCASP_SRCTL13_SRMOD, XMT );

//CSL_FINST( g_mcasp_regs->SRCTL11, MCASP_SRCTL11_SRMOD, XMT );

// pfunc
//------

CSL_FINST( g_mcasp_regs->PFUNC, MCASP_PFUNC_AFSX, MCASP );
CSL_FINST( g_mcasp_regs->PFUNC, MCASP_PFUNC_AHCLKX, MCASP );
CSL_FINST( g_mcasp_regs->PFUNC, MCASP_PFUNC_ACLKX, MCASP );
CSL_FINST( g_mcasp_regs->PFUNC, MCASP_PFUNC_AXR13, MCASP );
CSL_FINST( g_mcasp_regs->PFUNC, MCASP_PFUNC_AXR12, MCASP );

// pdir
//-----

CSL_FINST( g_mcasp_regs->PDIR, MCASP_PDIR_AFSX, OUTPUT );
CSL_FINST( g_mcasp_regs->PDIR, MCASP_PDIR_AHCLKX, OUTPUT );
CSL_FINST( g_mcasp_regs->PDIR, MCASP_PDIR_ACLKX, OUTPUT );
CSL_FINST( g_mcasp_regs->PDIR, MCASP_PDIR_AXR13, OUTPUT );

CSL_FINST( g_mcasp_regs->PDIR, MCASP_PDIR_AFSR, INPUT );
CSL_FINST( g_mcasp_regs->PDIR, MCASP_PDIR_AHCLKR, INPUT );
CSL_FINST( g_mcasp_regs->PDIR, MCASP_PDIR_ACLKR, INPUT );
CSL_FINST( g_mcasp_regs->PDIR, MCASP_PDIR_AXR12, INPUT );

// disble dit
CSL_FINST( g_mcasp_regs->DITCTL, MCASP_DITCTL_DITEN, DISABLE );

// loopback
//---------

CSL_FINST( g_mcasp_regs->DLBCTL, MCASP_DLBCTL_ORD, XMTEVEN );
CSL_FINST( g_mcasp_regs->DLBCTL, MCASP_DLBCTL_MODE, XMTCLK );
CSL_FINST( g_mcasp_regs->DLBCTL, MCASP_DLBCTL_DLBEN, ENABLE );

// amute not connected, dc's/disable
//----------------------------------

CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_XDMAERR, DISABLE );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_RDMAERR, DISABLE );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_XCKFAIL, DISABLE );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_RCKFAIL, DISABLE );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_XUNDRN, DISABLE );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_ROVRN, DISABLE );

CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_INSTAT, INACTIVE );

CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_INEN, DISABLE );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_INPOL, ACTHIGH );
CSL_FINST( g_mcasp_regs->AMUTE, MCASP_AMUTE_MUTEN, DISABLE );

 startup and run

// high frequency clock
//---------------------

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XHCLKRST) != CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->XGBLCTL, MCASP_XGBLCTL_XHCLKRST, ACTIVE );

      while( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XHCLKRST ) != CSL_MCASP_GBLCTL_XHCLKRST_ACTIVE );
}

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RHCLKRST) != CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->RGBLCTL, MCASP_RGBLCTL_RHCLKRST, ACTIVE );

      while ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RHCLKRST ) != CSL_MCASP_GBLCTL_RHCLKRST_ACTIVE );
}

// serial clocks
//--------------

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XCLKRST ) != CSL_MCASP_GBLCTL_XCLKRST_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->XGBLCTL, MCASP_XGBLCTL_XCLKRST, ACTIVE );

      while ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XCLKRST ) != CSL_MCASP_GBLCTL_XCLKRST_ACTIVE );
}

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RCLKRST ) != CSL_MCASP_GBLCTL_RCLKRST_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->RGBLCTL, MCASP_RGBLCTL_RCLKRST, ACTIVE );

      while ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RCLKRST ) != CSL_MCASP_GBLCTL_RCLKRST_ACTIVE );
}

// clear tx/rx status
//-------------------

g_mcasp_regs->XSTAT = 0x0000ffff;
g_mcasp_regs->RSTAT = 0x0000ffff;

// take serializers out of reset
//------------------------------

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XSRCLR ) != CSL_MCASP_GBLCTL_XSRCLR_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->XGBLCTL, MCASP_XGBLCTL_XSRCLR, ACTIVE );

      while ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XSRCLR ) != CSL_MCASP_GBLCTL_XSRCLR_ACTIVE );
}

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RSRCLR ) != CSL_MCASP_GBLCTL_RSRCLR_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->RGBLCTL, MCASP_RGBLCTL_RSRCLR, ACTIVE );

      while ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RSRCLR ) != CSL_MCASP_GBLCTL_RSRCLR_ACTIVE );
}

// write dummy value to tx serializer
//-----------------------------------

if ( CSL_FEXT( g_mcasp_regs->XSTAT, MCASP_XSTAT_XDATA ) == CSL_MCASP_XSTAT_XDATA_YES )
{
      cnt_tx++;

      g_mcasp_regs->XBUF13 = 0x11223344;
}

// release state machines from reset
//----------------------------------

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XSMRST ) != CSL_MCASP_GBLCTL_XSMRST_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->XGBLCTL, MCASP_XGBLCTL_XSMRST, ACTIVE );

      while ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XSMRST ) != CSL_MCASP_GBLCTL_XSMRST_ACTIVE );
}

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RSMRST ) != CSL_MCASP_GBLCTL_RSMRST_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->RGBLCTL, MCASP_RGBLCTL_RSMRST, ACTIVE );

      while( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RSMRST ) != CSL_MCASP_GBLCTL_RSMRST_ACTIVE );
}

// release sync generators from reset
//-----------------------------------

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XFRST ) != CSL_MCASP_GBLCTL_XFRST_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->XGBLCTL, MCASP_XGBLCTL_XFRST, ACTIVE );

      while ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_XFRST ) != CSL_MCASP_GBLCTL_XFRST_ACTIVE );
}

if ( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RFRST ) != CSL_MCASP_GBLCTL_RFRST_ACTIVE )
{
      CSL_FINST( g_mcasp_regs->RGBLCTL, MCASP_RGBLCTL_RFRST, ACTIVE );

      while( CSL_FEXT( g_mcasp_regs->GBLCTL, MCASP_GBLCTL_RFRST ) != CSL_MCASP_GBLCTL_RFRST_ACTIVE );
}

while (1)
{
      if ( CSL_FEXT( g_mcasp_regs->XSTAT, MCASP_XSTAT_XDATA ) == CSL_MCASP_XSTAT_XDATA_YES )
      {
          cnt_tx++;

          g_mcasp_regs->XBUF13 = 0x11223344;
      }

      if ( CSL_FEXT( g_mcasp_regs->RSTAT, MCASP_RSTAT_RDATA ) == CSL_MCASP_RSTAT_RDATA_YES )
      {
          g_data_in[ cnt_rx ] = g_mcasp_regs->RBUF12;

          if ( ++cnt_rx == DATA_IN )
          {
              cnt_rx = 0;
          }
      }
}